The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 09, 2022

Filed:

Dec. 19, 2018
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Hau Thanh Nguyen, San Jose, CA (US);

Woochan Kim, Sunnyvale, CA (US);

Yi Yan, Sunnyvale, CA (US);

Luu Thanh Nguyen, San Jose, CA (US);

Ashok Prabhu, San Jose, CA (US);

Anindya Poddar, Sunnyvale, CA (US);

Masamitsu Matsuura, Oita, JP;

Kengo Aoya, Oita, JP;

Mutsumi Masumoto, Oita, JP;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 23/528 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76816 (2013.01); H01L 21/76817 (2013.01); H01L 21/76897 (2013.01); H01L 23/3114 (2013.01); H01L 23/528 (2013.01); H01L 24/05 (2013.01); H01L 2224/02379 (2013.01); H01L 2224/04105 (2013.01); H01L 2924/14 (2013.01); H01L 2924/15172 (2013.01);
Abstract

An electronic device () includes a substrate () and an integrated circuit () provided on the substrate () having a surface facing away from the substrate (). An insulating layer () extends over the substrate () and around the integrated circuit () to define an interface () between the insulating layer () and the integrated circuit (). An electrically conductive via () is provided on the surface of the integrated circuit (). An insulating material () extends over the via () and includes an opening () exposing a portion of the via (). A repassivation member () extends over the insulating layer () and has a surface () aligned with the interface (). An electrically conductive redistribution member () is electrically connected to the via () and extends over the repassivation member () into contact with the insulating layer ().


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