The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 26, 2022
Filed:
Sep. 26, 2018
Intel Corporation, Santa Clara, CA (US);
Gilbert Dewey, Beaveton, OR (US);
Van H. Le, Portland, OR (US);
Abhishek Sharma, Hillsboro, OR (US);
Jack T. Kavalieros, Portland, OR (US);
Sean Ma, Portland, OR (US);
Seung Hoon Sung, Portland, OR (US);
Nazila Haratipour, Hillsboro, OR (US);
Tahir Ghani, Portland, OR (US);
Justin Weber, Portland, OR (US);
Shriram Shivaraman, Hillsboro, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Embodiments herein describe techniques for a transistor above the substrate. The transistor includes a first gate dielectric layer with a first gate dielectric material above a gate electrode, and a second dielectric layer with a second dielectric material above a portion of the first gate dielectric layer. A first portion of a channel layer overlaps with only the first gate dielectric layer, while a second portion of the channel layer overlaps with the first gate dielectric layer and the second dielectric layer. A first portion of a contact electrode overlaps with the first portion of the channel layer, and overlaps with only the first gate dielectric layer, while a second portion of the contact electrode overlaps with the second portion of the channel layer, and overlaps with the first gate dielectric layer and the second dielectric layer. Other embodiments may be described and/or claimed.