The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 12, 2022

Filed:

Sep. 27, 2017
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Abhishek A. Sharma, Hillsboro, OR (US);

Van H. Le, Beaverton, OR (US);

Jack T. Kavalieros, Portland, OR (US);

Tahir Ghani, Portland, OR (US);

Gilbert Dewey, Hillsboro, OR (US);

Shriram Shivaraman, Hillsboro, OR (US);

Inanc Meric, Portland, OR (US);

Benjamin Chu-Kung, Boise, ID (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/786 (2006.01); H01L 27/108 (2006.01); H01L 27/24 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/786 (2013.01); H01L 27/10805 (2013.01); H01L 27/2436 (2013.01); H01L 29/518 (2013.01); H01L 29/66765 (2013.01);
Abstract

Embodiments herein describe techniques for a semiconductor device, which may include a substrate, a metallic encapsulation layer above the substrate, and a gate electrode above the substrate and next to the metallic encapsulation layer. A channel layer may be above the metallic encapsulation layer and the gate electrode, where the channel layer may include a source area and a drain area. In addition, a source electrode may be coupled to the source area, and a drain electrode may be coupled to the drain area. Other embodiments may be described and/or claimed.


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