The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 12, 2022

Filed:

Aug. 09, 2018
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Debendra Mallik, Chandler, AZ (US);

Sanka Ganesan, Chandler, AZ (US);

Pilin Liu, Chandler, AZ (US);

Shawna Liff, Scottsdale, AZ (US);

Sri Chaitra Chavali, Chandler, AZ (US);

Sandeep Gaan, Phoenix, AZ (US);

Jimin Yao, Chandler, AZ (US);

Aastha Uppal, Chandler, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/28 (2006.01); H01L 23/34 (2006.01); H01L 23/538 (2006.01); H01L 23/532 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49816 (2013.01); H01L 23/28 (2013.01); H01L 23/34 (2013.01); H01L 23/5384 (2013.01); H01L 23/53228 (2013.01); H01L 23/53257 (2013.01);
Abstract

Embodiments include an electronics package and methods of forming such packages. In an embodiment, the electronics package comprises a first package substrate. In an embodiment, the first package substrate comprises, a die embedded in a mold layer, a thermal interface pad over a surface of the die, and a plurality of solder balls over the thermal interface pad. In an embodiment, the thermal interface pad and the solder balls are electrically isolated from circuitry of the electronics package. In an embodiment, the electronics package further comprises a second package substrate over the first package substrate.


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