The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 21, 2022
Filed:
Sep. 21, 2018
Intel Corporation, Santa Clara, CA (US);
Aaron Lilak, Beaverton, OR (US);
Stephen Cea, Hillsboro, OR (US);
Gilbert Dewey, Beaverton, OR (US);
Willy Rachmady, Beaverton, OR (US);
Roza Kotlyar, Portland, OR (US);
Rishabh Mehandru, Portland, OR (US);
Sean Ma, Portland, OR (US);
Ehren Mannebach, Beaverton, OR (US);
Anh Phan, Beaverton, OR (US);
Cheng-Ying Huang, Hillsboro, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A nanowire transistor structure has a first device region with a first body of semiconductor material having a first cross-sectional shape. A second device region has a second body with a second cross-sectional shape different from the first cross-sectional shape. The first device section is vertically above or below the second device section with the bodies extending horizontally between a source and drain. A first gate structure is wrapped around the first body and a second gate structure is wrapped around the second body. Differences in the geometries of the nanowires can be used to optimize performance in the first device section independently of the second device section.