The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 01, 2022

Filed:

Aug. 03, 2018
Applicant:

Nepes Co., Ltd., Chungcheongbuk-do, KR;

Inventors:

Yongtae Kwon, Cheongju-si, KR;

Eung Ju Lee, Cheongju-si, KR;

Yong Woon Yeo, Cheongju-si, KR;

Yun Mook Park, Cheongju-si, KR;

Hyo Young Kim, Cheongju-si, KR;

Jun Kyu Lee, Cheongju-si, KR;

Seok Hwi Cheon, Cheongju-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/538 (2006.01); G06K 9/00 (2022.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5386 (2013.01); G06K 9/00053 (2013.01); H01L 23/31 (2013.01); H01L 23/5384 (2013.01);
Abstract

Disclosed are a chip package capable of improving the strength of a package and simplifying a manufacturing process and a manufacturing method therefor. This invention may improve the durability of the package by further forming a reinforcing layer on a chip by using an adhesive layer and molding the chip and the reinforcing layer so as to be integrated by using a molding layer. Also, the strength of the package may be improved by having a structure in which solder balls are formed between a base substrate and a re-wiring layer and integrated with the molding layer, and a wiring layer may be formed directly on the molding layer by using polyimide (PI) as the molding layer without using a separate insulating layer formed on the molding layer as in the conventional art.


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