The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 21, 2021

Filed:

Dec. 22, 2014
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Nadia M. Rahhal-Orabi, Lake Oswego, OR (US);

Tahir Ghani, Portland, OR (US);

Willy Rachmady, Beaverton, OR (US);

Matthew V. Metz, Portland, OR (US);

Jack T. Kavalieros, Portland, OR (US);

Gilbert Dewey, Hillsboro, OR (US);

Anand S. Murthy, Portland, OR (US);

Chandra S. Mohapatra, Beaverton, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/28 (2006.01); H01L 29/423 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66545 (2013.01); H01L 21/28114 (2013.01); H01L 29/42376 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01);
Abstract

Systems and methods of optimizing a gate profile for performance and gate fill are disclosed. A semiconductor device having an optimized gate profile includes a semiconductor substrate and a fin extending above the semiconductor substrate. A pair of source and drain regions are disposed on opposite sides of a channel region. A gate stack is disposed over the channel region, where the gate stack includes a top portion separated from a bottom portion by a tapered portion. The top portion and at least a portion of the tapered portion are disposed above the fin.


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