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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11152330 B1

PDFFull Text
Date of Patent:
Oct. 19, 2021

Filed:

Apr. 16, 2019

Semiconductor package structure and method for forming the same

Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Cheng-Chieh Li, Hsinchu, TW;

Pu Wang, Hsinchu, TW;

Chih-Wei Wu, Zhuangwei Township, Yilan County, TW;

Ying-Ching Shih, Hsinchu, TW;

Szu-Wei Lu, Hsinchu, TW;

Assignee:

TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu, TW;

Attorney:

McClure, Qualey & Rodack, LLP

Primary Examiner:

Moazzam Hossain

Int. Cl.
CPC ...
H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 21/683 (2006.01); H01L 21/78 (2006.01); H01L 25/065 (2006.01); H01L 23/367 (2006.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0652 (2013.01); H01L 21/4882 (2013.01); H01L 21/565 (2013.01); H01L 21/6835 (2013.01); H01L 21/78 (2013.01); H01L 23/3675 (2013.01); H01L 25/50 (2013.01); H01L 2221/68327 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06555 (2013.01); H01L 2225/06586 (2013.01); H01L 2225/06589 (2013.01);
Abstract

A method for forming a semiconductor package structure includes stacking chips to form a chip stack over an interposer. The method also includes disposing a semiconductor die over the interposer. The method also includes filling a first encapsulating layer between the chips and surrounding the chip stack and the semiconductor die. The method also includes forming a second encapsulating layer covering the chip stack and the semiconductor die. The first encapsulating layer fills the gap between the chip stack and the semiconductor die.

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