The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 19, 2021
Filed:
Dec. 28, 2016
Intel Corporation, Santa Clara, CA (US);
Manish Chandhok, Beaverton, OR (US);
Sudipto Naskar, Portland, OR (US);
Stephanie A. Bojarski, Sherwood, OR (US);
Kevin Lin, Beaverton, OR (US);
Marie Krysak, Portland, OR (US);
Tristan A. Tronic, Aloha, OR (US);
Hui Jae Yoo, Hilsboro, OR (US);
Jeffery D. Bielefeld, Forest Grove, OR (US);
Jessica M. Torres, Portland, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
An integrated circuit die, a semiconductor structure, and a method of fabricating the semiconductor structure are disclosed. The integrated circuit die includes a substrate and a first anchor and a second anchor disposed on the substrate in a first plane. The integrated circuit die also includes a first wire disposed on the first anchor in the first plane, a third wire disposed on the second anchor in the first plane, and a second wire and a fourth wire suspended above the substrate in the first plane. The second wire is disposed between the first wire and the third wire and the third wire is disposed between the second wire and the fourth wire. The integrated circuit die further includes a dielectric material disposed between upper portions of the first wire, the second wire, the third wire, and the fourth wire to encapsulate an air gap.