The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 17, 2021
Filed:
Nov. 26, 2019
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Hsia-Wei Chen, Taipei, TW;
Chih-Yang Chang, Yuanlin Township, TW;
Chin-Chieh Yang, New Taipei, TW;
Jen-Sheng Yang, Keelung, TW;
Kuo-Chi Tu, Hsin-Chu, TW;
Wen-Ting Chu, Kaohsiung, TW;
Yu-Wen Liao, New Taipei, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Abstract
The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a memory device over a substrate and forming an inter-level dielectric (ILD) layer over the memory device. The ILD layer is selectively etched to define a first cavity that exposes a top of the memory device and to define a second cavity that is laterally separated from the first cavity by the ILD layer. The second cavity is defined by a smooth sidewall of the ILD layer that extends between upper and lower surfaces of the ILD layer. A conductive material is formed within the first cavity and the second cavity.