The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 01, 2021

Filed:

Dec. 31, 2016
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Seung Hoon Sung, Portland, OR (US);

Dipanjan Basu, Hillsboro, OR (US);

Glenn A. Glass, Portland, OR (US);

Harold W. Kennel, Portland, OR (US);

Ashish Agrawal, Hillsboro, OR (US);

Benjamin Chu-Kung, Portland, OR (US);

Anand S. Murthy, Portland, OR (US);

Jack T. Kavalieros, Portland, OR (US);

Tahir Ghani, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/08 (2006.01); H01L 29/78 (2006.01); H01L 21/02 (2006.01); H01L 29/167 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0847 (2013.01); H01L 21/0262 (2013.01); H01L 21/02579 (2013.01); H01L 29/167 (2013.01); H01L 29/66636 (2013.01); H01L 29/7834 (2013.01);
Abstract

An apparatus is provided which comprises: a semiconductor region on a substrate, a gate stack on the semiconductor region, a source region of doped semiconductor material on the substrate adjacent a first side of the semiconductor region, a drain region of doped semiconductor material on the substrate adjacent a second side of the semiconductor region, and a transition region in the drain region, adjacent the semiconductor region, wherein the transition region comprises varying dopant concentrations that increase in a direction away from the semiconductor region. Other embodiments are also disclosed and claimed.


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