The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 20, 2021

Filed:

Nov. 24, 2015
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Pramod Malatkar, Chandler, AZ (US);

Kyle Yazzie, Chandler, AZ (US);

Naga Sivakumar Yagnamurthy, Chandler, AZ (US);

Richard J. Harries, Chandler, AZ (US);

Dilan Seneviratne, Chandler, AZ (US);

Praneeth Akkinepally, Chandler, AZ (US);

Xuefei Wan, Chandler, AZ (US);

Yonggang Li, Chandler, AZ (US);

Robert L. Sankman, Phoenix, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/31 (2006.01); H01L 23/34 (2006.01); H01L 23/48 (2006.01); H01L 25/10 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3128 (2013.01); H01L 23/315 (2013.01); H01L 23/3135 (2013.01); H01L 23/3142 (2013.01); H01L 23/34 (2013.01); H01L 23/48 (2013.01); H01L 23/562 (2013.01); H01L 25/105 (2013.01); H01L 23/49816 (2013.01); H01L 23/5389 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 24/81 (2013.01); H01L 24/97 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/81203 (2013.01); H01L 2225/1023 (2013.01); H01L 2225/1058 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/10253 (2013.01); H01L 2924/1433 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/15331 (2013.01); H01L 2924/181 (2013.01); H01L 2924/351 (2013.01); H01L 2924/3511 (2013.01);
Abstract

An electronic package that includes a substrate and an electronic component attached to the substrate. A laminated layer is attached to an upper surface of the substrate such that the laminated layer covers the electronic component. The electronic package may further include a stiffener mounted on the laminated layer where the stiffener is over the electronic component.


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