The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 26, 2021

Filed:

Sep. 22, 2019
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Hsia-Wei Chen, Taipei, TW;

Chih-Yang Chang, Yuanlin Township, TW;

Chin-Chieh Yang, New Taipei, TW;

Jen-Sheng Yang, Keelung, TW;

Kuo-Chi Tu, Hsin-Chu, TW;

Wen-Ting Chu, Kaohsiung, TW;

Yu-Wen Liao, New Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/24 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 45/00 (2006.01); H01L 27/105 (2006.01); H01L 27/102 (2006.01);
U.S. Cl.
CPC ...
H01L 27/2463 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 27/1025 (2013.01); H01L 27/1052 (2013.01); H01L 27/2436 (2013.01); H01L 45/1233 (2013.01); H01L 45/146 (2013.01); H01L 45/1608 (2013.01); H01L 45/1675 (2013.01);
Abstract

The present disclosure, in some embodiments, relates to an integrated circuit. The integrated circuit has a first inter-level dielectric (ILD) layer over a substrate. A lower electrode is over the first ILD layer, a data storage structure is over the lower electrode, and an upper electrode is over the data storage structure. An upper interconnect wire directly contacts an entirety of an upper surface of the upper electrode. A conductive via directly contacts an upper surface of the upper interconnect wire. The conductive via has an outermost sidewall that is directly over the upper surface of the upper interconnect wire.


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