The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 22, 2020
Filed:
Apr. 01, 2019
Cmos implementation of germanium and iii-v nanowires and nanoribbons in gate-all-around architecture
Intel Corporation, Santa Clara, CA (US);
Marko Radosavljevic, Portland, OR (US);
Ravi Pillarisetty, Portland, OR (US);
Gilbert Dewey, Beaverton, OR (US);
Niloy Mukherjee, San Ramon, CA (US);
Jack Kavalieros, Portland, OR (US);
Willy Rachmady, Beaverton, OR (US);
Van Le, Portland, OR (US);
Benjamin Chu-Kung, Portland, OR (US);
Matthew Metz, Portland, OR (US);
Robert Chau, Beaverton, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Architectures and techniques for co-integration of heterogeneous materials, such as group III-V semiconductor materials and group IV semiconductors (e.g., Ge) on a same substrate (e.g. silicon). In embodiments, multi-layer heterogeneous semiconductor material stacks having alternating nanowire and sacrificial layers are employed to release nanowires and permit formation of a coaxial gate structure that completely surrounds a channel region of the nanowire transistor. In embodiments, individual PMOS and NMOS channel semiconductor materials are co-integrated with a starting substrate having a blanket layers of alternating Ge/III-V layers. In embodiments, vertical integration of a plurality of stacked nanowires within an individual PMOS and individual NMOS device enable significant drive current for a given layout area.