The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 18, 2020
Filed:
Jul. 19, 2019
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Hung-Chun Wang, Taichung, TW;
Ching-Hsu Chang, Taipei County, TW;
Chun-Hung Wu, Hsinchu, TW;
Cheng Kun Tsai, Hsinchu, TW;
Feng-Ju Chang, Hsinchu, TW;
Feng-Lung Lin, Hsinchu County, TW;
Ming-Hsuan Wu, Hsinchu County, TW;
Ping-Chieh Wu, Hsinchu County, TW;
Ru-Gun Liu, Hsinchu County, TW;
Wen-Chun Huang, Tainan, TW;
Wen-Hao Liu, Hsinchu County, TW;
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsin-Chu, TW;
Abstract
An integrated circuit (IC) manufacturing method includes receiving an IC design layout having IC regions separate from each other. Each of the IC regions includes an initial IC pattern that is substantially identical among the IC regions. The method further includes identifying a group of IC regions from the IC regions. All IC regions in the group have a substantially same location effect, which is introduced by global locations of the IC regions on the IC design layout. The method further includes performing a correction process to a first IC region in the group, modifying the initial IC pattern in the first IC region into a first corrected IC pattern. The correction process includes using a computer program to correct location effect. The method further includes replacing the initial IC pattern in a second IC region in the group with the first corrected IC pattern.