The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 26, 2020

Filed:

Oct. 27, 2017
Applicant:

Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;

Inventors:

Chuei-Tang Wang, Taichung, TW;

Chih-Chieh Chang, Hsinchu, TW;

Yu-Kuang Liao, Hsinchu, TW;

Hsing-Kuo Hsia, Hsinchu County, TW;

Chih-Yuan Chang, Hsinchu, TW;

Jeng-Shien Hsieh, Kaohsiung, TW;

Chen-Hua Yu, Hsinchu, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 21/304 (2006.01); H01L 21/306 (2006.01); H01L 21/44 (2006.01); H01L 23/31 (2006.01); H01L 23/522 (2006.01); H01L 23/498 (2006.01); H01L 25/00 (2006.01); H01L 21/683 (2006.01);
U.S. Cl.
CPC ...
H01L 24/17 (2013.01); H01L 21/304 (2013.01); H01L 21/30604 (2013.01); H01L 21/44 (2013.01); H01L 21/6835 (2013.01); H01L 23/3107 (2013.01); H01L 23/3128 (2013.01); H01L 23/49811 (2013.01); H01L 23/5226 (2013.01); H01L 24/03 (2013.01); H01L 24/09 (2013.01); H01L 24/11 (2013.01); H01L 25/00 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 24/81 (2013.01); H01L 24/92 (2013.01); H01L 2221/6834 (2013.01); H01L 2221/68327 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/81005 (2013.01); H01L 2224/92125 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06534 (2013.01); H01L 2225/06572 (2013.01); H01L 2924/15311 (2013.01);
Abstract

A semiconductor package includes an interconnect structure having a first surface and a second surface opposite to the first surface, at least one optical chip over the first surface of the interconnect structure and electrically coupled to the interconnect structure, an insulating layer contacting the second surface of the interconnect structure, and a molding compound over the first surface of the interconnect structure. The insulating layer includes a third surface facing the second surface of the interconnect structure and a fourth surface opposite to the third surface. At least an edge of the optical chip is covered by the molding compound.


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