The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 17, 2020

Filed:

Dec. 11, 2018
Applicant:

Micromaterials Llc, Wilmington, DE (US);

Inventors:

Yung-Chen Lin, Gardena, CA (US);

Qingjun Zhou, San Jose, CA (US);

Ying Zhang, Santa Clara, CA (US);

Ho-yung David Hwang, Cupertino, CA (US);

Uday Mitra, Cupertino, CA (US);

Regina Freed, Los Altos, CA (US);

Assignee:

Micromaterials LLC, Wilmington, DE (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 21/311 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76897 (2013.01); H01L 21/76808 (2013.01); H01L 21/76831 (2013.01); H01L 21/76883 (2013.01); H01L 21/31144 (2013.01); H01L 21/76834 (2013.01); H01L 2221/1031 (2013.01); H01L 2221/1036 (2013.01);
Abstract

Methods of forming a self-aligned via comprising recessing a first metallization layer comprising a set of first conductive lines that extend along a first direction on a first insulating layer on a substrate. A second insulating layer is formed on the first insulating layer. A via is formed through the second insulating layer to one of the first conductive lines. Semiconductor devices comprising the self-aligned via and apparatus for forming the self-aligned via are also disclosed.


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