The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 18, 2020
Filed:
Aug. 22, 2018
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Hsia-Wei Chen, Taipei, TW;
Chih-Yang Chang, Yuanlin Township, TW;
Chin-Chieh Yang, New Taipei, TW;
Jen-Sheng Yang, Keelung, TW;
Kuo-Chi Tu, Hsin-Chu, TW;
Wen-Ting Chu, Kaohsiung, TW;
Yu-Wen Liao, New Taipei, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Abstract
The present disclosure relates to a method of forming an integrated circuit. In some embodiments, the method may be performed by forming a lower interconnect structure within a first inter-level dielectric (ILD) layer over an upper surface of a substrate, and forming a resistive random access memory (RRAM) device over the lower interconnect structure. A second ILD layer is formed over the RRAM device. The second ILD layer is patterned to remove a part of the second ILD layer that defines a cavity. The cavity vertically extends from an upper surface of the second ILD layer to an upper surface of the RRAM device and laterally extends past opposing sidewalls of the RRAM device. An upper interconnect wire is formed within the cavity.