The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 21, 2020
Filed:
Dec. 24, 2015
Brian S. Doyle, Portland, OR (US);
Elijah V. Karpov, Portland, OR (US);
Kaan Oguz, Portland, OR (US);
Kevin P. O'brien, Portland, OR (US);
Charles C. Kuo, Hillsboro, OR (US);
Mark L. Doczy, Beaverton, OR (US);
Uday Shah, Portland, OR (US);
Yih Wang, Portland, OR (US);
Brian S. Doyle, Portland, OR (US);
Elijah V. Karpov, Portland, OR (US);
Kaan Oguz, Portland, OR (US);
Kevin P. O'Brien, Portland, OR (US);
Charles C. Kuo, Hillsboro, OR (US);
Mark L. Doczy, Beaverton, OR (US);
Uday Shah, Portland, OR (US);
Yih Wang, Portland, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Memory cells with improved tunneling magnetoresistance ratio (TMR) are disclosed. In some embodiments such devices may include a magnetoresistive tunnel junction (MTJ) element coupled in series with a tunneling magnetoresistance enhancement element (TMRE). The MTJ element and TMRE may each be configured to transition between high and low resistance states, e.g., in response to a voltage. In some embodiments, the MTJ and TMRE are configure such that when a read voltage is applied to the cell while the MTJ is in its low resistance state the TMRE is driven to is low resistance state, and when such voltage is applied while the MTJ is in its high resistance state, the TMRE remains in its high resistance state. Devices and systems including such memory cells are also disclosed.