The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 24, 2019

Filed:

Dec. 24, 2014
Applicants:

Niloy Mukherjee, Portland, OR (US);

Ravi Pillarisetty, Portland, OR (US);

Prashant Majhi, San Jose, CA (US);

Uday Shah, Portland, OR (US);

Ryan E Arch, Hillsboro, OR (US);

Markus Kuhn, Hillsboro, OR (US);

Justin S. Brockman, Portland, OR (US);

Huiying Liu, Portland, OR (US);

Elijah V Karpov, Portland, OR (US);

Kaan Oguz, Beaverton, OR (US);

Brian S. Doyle, Portland, OR (US);

Robert S. Chau, Beaverton, OR (US);

Inventors:

Niloy Mukherjee, Portland, OR (US);

Ravi Pillarisetty, Portland, OR (US);

Prashant Majhi, San Jose, CA (US);

Uday Shah, Portland, OR (US);

Ryan E Arch, Hillsboro, OR (US);

Markus Kuhn, Hillsboro, OR (US);

Justin S. Brockman, Portland, OR (US);

Huiying Liu, Portland, OR (US);

Elijah V Karpov, Portland, OR (US);

Kaan Oguz, Beaverton, OR (US);

Brian S. Doyle, Portland, OR (US);

Robert S. Chau, Beaverton, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 45/00 (2006.01);
U.S. Cl.
CPC ...
H01L 45/1633 (2013.01); H01L 45/08 (2013.01); H01L 45/126 (2013.01); H01L 45/145 (2013.01); H01L 45/1608 (2013.01); H01L 45/1616 (2013.01);
Abstract

Resistive memory cells, precursors thereof, and methods of making resistive memory cells are described. In some embodiments, the resistive memory cells are formed from a resistive memory precursor that includes a switching layer precursor containing a plurality of oxygen vacancies that are present in a controlled distribution therein, optionally without the use of an oxygen exchange layer. In these or other embodiments, the resistive memory precursors described may include a second electrode formed on a switching layer precursor, wherein the second electrode is includes a second electrode material that is conductive but which does not substantially react with oxygen. Devices including resistive memory cells are also described.


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