The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 24, 2019

Filed:

Dec. 23, 2011
Applicants:

Annalisa Cappellani, Portland, OR (US);

Kelin J. Kuhn, Aloha, OR (US);

Rafael Rios, Portland, OR (US);

Gopinath Bhimarasetti, Portland, OR (US);

Tahir Ghani, Portland, OR (US);

Seiyon Kim, Portland, OR (US);

Inventors:

Annalisa Cappellani, Portland, OR (US);

Kelin J. Kuhn, Aloha, OR (US);

Rafael Rios, Portland, OR (US);

Gopinath Bhimarasetti, Portland, OR (US);

Tahir Ghani, Portland, OR (US);

Seiyon Kim, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/775 (2006.01); H01L 21/02 (2006.01); H01L 27/088 (2006.01); B82Y 10/00 (2011.01); B82Y 40/00 (2011.01); H01L 29/66 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/78 (2006.01); H01L 29/786 (2006.01); H01L 29/16 (2006.01); B82Y 99/00 (2011.01);
U.S. Cl.
CPC ...
H01L 27/0886 (2013.01); B82Y 10/00 (2013.01); B82Y 40/00 (2013.01); H01L 21/02587 (2013.01); H01L 29/0673 (2013.01); H01L 29/42392 (2013.01); H01L 29/66439 (2013.01); H01L 29/775 (2013.01); H01L 29/785 (2013.01); H01L 29/78696 (2013.01); B82Y 99/00 (2013.01); H01L 29/16 (2013.01); H01L 2924/0002 (2013.01);
Abstract

Semiconductor devices having modulated nanowire counts and methods to form such devices are described. For example, a semiconductor structure includes a first semiconductor device having a plurality of nanowires disposed above a substrate and stacked in a first vertical plane with a first uppermost nanowire. A second semiconductor device has one or more nanowires disposed above the substrate and stacked in a second vertical plane with a second uppermost nanowire. The second semiconductor device includes one or more fewer nanowires than the first semiconductor device. The first and second uppermost nanowires are disposed in a same plane orthogonal to the first and second vertical planes.


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