The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 06, 2019

Filed:

Jun. 26, 2015
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Glenn A. Glass, Portland, OR (US);

Anand S. Murthy, Portland, OR (US);

Daniel B. Aubertine, North Plains, OR (US);

Tahir Ghani, Portland, OR (US);

Jack T. Kavalieros, Portland, OR (US);

Benjamin Chu-Kung, Portland, OR (US);

Chandra S. Mohapatra, Beaverton, OR (US);

Karthik Jambunathan, Hillsboro, OR (US);

Gilbert Dewey, Hillsboro, OR (US);

Willy Rachmady, Beaverton, OR (US);

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 29/78 (2006.01); H01L 21/84 (2006.01); H01L 29/66 (2006.01); H01L 21/762 (2006.01); H01L 29/06 (2006.01); H01L 29/161 (2006.01); H01L 29/20 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1211 (2013.01); H01L 21/76224 (2013.01); H01L 21/845 (2013.01); H01L 29/0649 (2013.01); H01L 29/161 (2013.01); H01L 29/20 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/78 (2013.01); H01L 29/0673 (2013.01);
Abstract

Techniques are disclosed for customization of fin-based transistor devices to provide a diverse range of channel configurations and/or material systems, and within the same integrated circuit die. In accordance with an embodiment, sacrificial fins are cladded and then removed thereby leaving the cladding layer as a pair of standalone fins. Once the sacrificial fin areas are filled back in with a suitable insulator, the resulting structure is fin-on-insulator. The new fins can be configured with any materials by using such a cladding-on-core approach. The resulting fin-on-insulator structure is favorable, for instance, for good gate control while eliminating or otherwise reducing sub-channel source-to-drain (or drain-to-source) leakage current. In addition, parasitic capacitance from channel-to-substrate is significantly reduced. The sacrificial fins can be thought of as cores and can be implemented, for example, with material native to the substrate or a replacement material that enables low-defect exotic cladding materials combinations.


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