The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 23, 2019

Filed:

Feb. 15, 2016
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Hung-Chun Wang, Taichung, TW;

Ching-Hsu Chang, Taipei County, TW;

Chun-Hung Wu, Hsinchu, TW;

Cheng Kun Tsai, Hsinchu, TW;

Feng-Ju Chang, Hsinchu, TW;

Feng-Lung Lin, Hsinchu County, TW;

Ming-Hsuan Wu, Hsinchu County, TW;

Ping-Chieh Wu, Hsinchu County, TW;

Ru-Gun Liu, Hsinchu County, TW;

Wen-Chun Huang, Tainan, TW;

Wen-Hao Liu, Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G03F 1/00 (2012.01); G03F 7/20 (2006.01); G03F 1/36 (2012.01); H01L 27/02 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5081 (2013.01); G03F 1/36 (2013.01); G03F 7/70441 (2013.01); G06F 17/5068 (2013.01); G06F 2217/12 (2013.01); H01L 27/0207 (2013.01);
Abstract

Provided is an integrated circuit (IC) manufacturing method. The method includes receiving an IC design layout, wherein the IC design layout includes multiple IC regions and each of the IC regions includes an initial IC pattern. The method further includes performing a correction process to a first IC region, thereby modifying the initial IC pattern in the first IC region to result in a first corrected IC pattern in the first IC region, wherein the correction process includes location effect correction. The method further includes replacing the initial IC pattern in a second IC region with the first corrected IC pattern.


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