The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 04, 2019
Filed:
Jul. 20, 2017
Efficient Power Conversion Corporation, El Segundo, CA (US);
Jianjun Cao, Torrance, CA (US);
Robert Beach, La Crescenta, CA (US);
Alexander Lidow, Santa Monica, CA (US);
Alana Nakata, Redondo Beach, CA (US);
Guangyuan Zhao, Torrance, CA (US);
Yanping Ma, Torrance, CA (US);
Robert Strittmatter, Tujunga, CA (US);
Michael A. de Rooij, Palm Springs, CA (US);
Chunhua Zhou, Torrance, CA (US);
Seshadri Kolluri, San Jose, CA (US);
Fang-Chang Liu, Toufen Township, TW;
Ming-Kun Chiang, Hsinchu, TW;
Jiali Cao, Torrance, CA (US);
Agus Jauhar, Hsinchu, TW;
Efficient Power Conversion Corporation, El Segundo, CA (US);
Abstract
A GaN transistor with polysilicon layers for creating additional components for an integrated circuit and a method for manufacturing the same. The GaN device includes an EPI structure and an insulating material disposed over EPI structure. Furthermore, one or more polysilicon layers are disposed in the insulating material with the polysilicon layers having one or more n-type regions and p-type regions. The device further includes metal interconnects disposed on the insulating material and vias disposed in the insulating material layer that connect source and drain metals to the n-type and p-type regions of the polysilicon layer.