The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 18, 2018
Filed:
Aug. 17, 2016
International Business Machines Corporation, Armonk, NY (US);
Globalfoundries, Inc., Grand Cayman Islands, KY;
Stmicroelectronics, Inc., Coppell, TX (US);
Shyng-Tsong Chen, Rensselaer, NY (US);
Cheng Chi, Jersey City, NJ (US);
Chi-Chun Liu, Altamont, NY (US);
Sylvie M. Mignot, Slingerlands, NY (US);
Yann A. Mignot, Slingerlands, NY (US);
Hosadurga K. Shobha, Niskayuna, NY (US);
Terry A. Spooner, Clifton Park, NY (US);
Wenhui Wang, Clifton Park, NY (US);
Yongan Xu, Niskayuna, NY (US);
International Business Machines Corporation, Armonk, NY (US);
GLOBALFOUNDRIES, INC., Grand Cayman Islands, KS (US);
STMicroelectronics, Inc., Coppell, TX (US);
Abstract
A method of forming a via to an underlying layer of a semiconductor device is provided. The method may include forming a pillar over the underlying layer using a sidewall image transfer process. A dielectric layer is formed over the pillar and the underlying layer; and a via mask patterned over the dielectric layer, the via mask having a mask opening at least partially overlapping the pillar. A via opening is etched in the dielectric layer using the via mask, the mask opening defining a first lateral dimension of the via opening in a first direction and the pillar defining a second lateral dimension of the via opening in a second direction different than the first direction. The via opening is filled with a conductor to form the via. A semiconductor device and via structure are also provided.