The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 06, 2018
Filed:
Nov. 30, 2016
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Jeng-Shyan Lin, Tainan, TW;
Dun-Nian Yaung, Taipei, TW;
Jen-Cheng Liu, Hsin-Chu, TW;
Hsun-Ying Huang, Tainan, TW;
Wei-Chih Weng, Tainan, TW;
Yu-Yang Shen, Kaohsiung, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Abstract
The present disclosure relates to a method of forming a multi-dimensional integrated chip having tiers connected in a front-to-back configuration, and an associated apparatus. In some embodiments, the method is performed by forming one or more semiconductor devices within a first substrate, forming one or more image sensing elements within a second substrate, and bonding a first dielectric structure over the first substrate to a back-side of the second substrate by way of a bonding structure. An inter-tier interconnect structure, comprising a plurality of different segments, respectively having sidewalls with different sidewall angles, is formed to extend through the bonding structure and the second substrate. The inter-tier interconnect structure is configured to electrically couple a first metal interconnect layer over the first substrate to a second metal interconnect layer over the second substrate.