The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 09, 2018
Filed:
Jul. 08, 2013
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Shu-Ting Tsai, Kaohsiung, TW;
Jeng-Shyan Lin, Tainan, TW;
Dun-Nian Yaung, Taipei, TW;
Jen-Cheng Liu, Hsin-Chu, TW;
Feng-Chi Hung, Chu-Bei, TW;
Chih-Hui Huang, Yongkang, TW;
Sheng-Chau Chen, Kaohsiung, TW;
Shih-Pei Chou, Tainan, TW;
Chia-Chieh Lin, Kaohsiung, TW;
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsin-Chu, TW;
Abstract
A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element. The first substrate includes a dielectric block in the first substrate; and a plurality of first conductive features formed in first inter-metal dielectric layers over the first substrate. The stacked IC device also includes a second semiconductor element bonded on the first semiconductor element. The second semiconductor element includes a second substrate and a plurality of second conductive features formed in second inter-metal dielectric layers over the second substrate. The stacked IC device also includes a conductive deep-interconnection-plug coupled between the first conductive features and the second conductive features. The conductive deep-interconnection-plug is isolated by dielectric block, the first inter-metal-dielectric layers and the second inter-metal-dielectric layers.