The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 25, 2018
Filed:
Dec. 13, 2017
Dialog Semiconductor (Uk) Limited, London, GB;
Ian Kent, Chippenham, GB;
Rajesh Subraya Aiyandra, Denkendorf, DE;
Jesus Mennen Belonio, Jr., Neubiberg, DE;
Habeeb Mohiuddin Mohammed, Weilheim, DE;
Domingo Jr. Maggay, Bulacan, PH;
Robert Lamoon, Portishead, GB;
Ernesto Gutierrez, III, Swindon, GB;
Dialog Semiconductor (UK) Limited, London, GB;
Abstract
A wafer level chip scale package is described. At least one redistribution layer is connected to a wafer through an opening through a first polymer layer to a metal pad on a top surface of the wafer wherein the redistribution layer has a roughened top surface and wherein holes are formed through the at least one redistribution layer in an area where the redistribution layer has an area exceeding 0.2 mm. At least one UBM layer contacts the at least one redistribution layer through an opening in a second polymer layer wherein the second polymer layer contacts the first polymer layer within the holes promoting cohesion between the first and second polymer layers and wherein the roughened top surface promotes adhesion between the at least one redistribution layer and the second polymer layer.