The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 24, 2018
Filed:
Dec. 31, 2014
Stmicroelectronics, Inc., Coppell, TX (US);
Globalfoundries Inc., Grand Cayman, KY;
International Business Machines Corporation, Armonk, NY (US);
Pierre Morin, Albany, NY (US);
Kangguo Cheng, Schenectady, NY (US);
Jody Fronheiser, Delmar, NY (US);
Xiuyu Cai, Niskayuna, NY (US);
Juntao Li, Cohoes, NY (US);
Shogo Mochizuki, Clifton Park, NY (US);
Ruilong Xie, Schenectady, NY (US);
Hong He, Schenectady, NY (US);
Nicolas Loubet, Guilderland, NY (US);
STMICROELECTRONICS, INC., Coppell, TX (US);
GLOBALFOUNDRIES INC., Grand Cayman, KY;
INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US);
Abstract
A modified silicon substrate having a substantially defect-free strain relaxed buffer layer of SiGe is suitable for use as a foundation on which to construct a high performance CMOS FinFET device. The substantially defect-free SiGe strain-relaxed buffer layer can be formed by making cuts in, or segmenting, a strained epitaxial film, causing edges of the film segments to experience an elastic strain relaxation. When the segments are small enough, the overall film is relaxed so that the film is substantially without dislocation defects. Once the substantially defect-free strain-relaxed buffer layer is formed, strained channel layers can be grown epitaxially from the relaxed SRB layer. The strained channel layers are then patterned to create fins for a FinFET device. In one embodiment, dual strained channel layers are formed—a tensilely strained layer for NFET devices, and a compressively strained layer for PFET devices.