Hsinchu, Taiwan

Yung-Sheng Lin

This inventor holds 15 USPTO granted patents and 8 published patent applications, primarily in Semiconductor Packaging. Top assignee: Taiwan Semiconductor Manufacturing Comp. Ltd.. Active years: 2022-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Yung-Sheng Lin. Retrieved from https://idiyas.com/inventor/yung-sheng-lin-p3blnsi6

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 15 

% Patents Active = 100.0

Average Co-Inventor Count = 6.1

ph-index = 1

Forward Citations = 2(Granted Patents)


Location History:

  • Hsinchu County, TW (2023)
  • Hsinchu, TW (2022 - 2024)

Company Filing History:


Years Active: 2022-2026

Loading Chart...
Areas of Expertise:
Semiconductor Device
Conductive Bumps
Chip Structure
Redistribution Lines
Protection Layers
Bump Structure
Formation Method
Device Structure
3D Integration
Thermal Management
Interconnects
15 patents (USPTO):Explore Patents

Title: Yung-Sheng Lin: Innovator in Semiconductor Technology

Introduction

Yung-Sheng Lin is a prominent inventor based in Hsinchu, Taiwan. He has made significant contributions to the field of semiconductor technology, holding a total of 12 patents. His innovative work has advanced the manufacturing processes of semiconductor devices, showcasing his expertise and creativity.

Latest Patents

Among his latest patents is a method for forming redistribution lines with protection layers. This method involves creating a metal seed layer over a first conductive feature of a wafer, followed by the formation of a patterned photo resist. The process includes forming a second conductive feature in an opening in the patterned photo resist and heating the wafer to generate a gap between the second conductive feature and the patterned photo resist. A protection layer is then plated on the second conductive feature, and the patterned photo resist is removed, along with etching the metal seed layer.

Another notable patent is related to a bump structure and the method of making the same. In this method, first conductive layers are formed over a substrate, and a first photoresist layer is applied. The first conductive layers are etched using the first photoresist layer as a mask, creating an island pattern separated from a bus bar pattern by a ring-shaped groove. A connection pattern is established to link the island and bus bar patterns, followed by the formation of second conductive layers on the island pattern. The process concludes with the removal of the second photoresist layer and the connection pattern, resulting in a bump structure.

Career Highlights

Yung-Sheng Lin is currently employed at Taiwan Semiconductor Manufacturing Company Limited, a leading firm in the semiconductor industry. His work has been instrumental in enhancing the efficiency and effectiveness of semiconductor manufacturing processes.

Collaborations

Throughout his career, Yung-Sheng Lin has collaborated with notable colleagues, including Ming-Da Cheng and Wen-Hsiung Lu. These collaborations have contributed to the advancement of innovative technologies in the semiconductor field.

Conclusion

Yung-Sheng Lin's contributions to semiconductor technology through his patents and collaborations highlight his role as a key innovator in the industry. His work continues to influence the development of advanced manufacturing techniques, solidifying his legacy as a leading inventor.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…