The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 16, 2025

Filed:

Sep. 22, 2023
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Yung-Sheng Lin, Hsinchu County, TW;

Cheng-Lung Yang, Kaohsiung, TW;

Chin-Yu Ku, Hsinchu, TW;

Ming-Da Cheng, Taoyuan, TW;

Wen-Hsiung Lu, Tainan, TW;

Tang-Wei Huang, Hsinchu, TW;

Fu Wei Liu, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/495 (2006.01); H01L 21/48 (2006.01); H01L 21/768 (2006.01); H01L 23/00 (2006.01); H01L 23/48 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49548 (2013.01); H01L 21/4821 (2013.01); H01L 21/76898 (2013.01); H01L 23/481 (2013.01); H01L 23/49565 (2013.01); H01L 23/562 (2013.01);
Abstract

A semiconductor device and a method of forming the same are provided. The semiconductor device includes at least one substrate and an interconnection structure. The at least one substrate has a cavity partially defined by an inner sidewall of the at least one substrate and a channel disposed at a bottom of the at least one substrate. The channel laterally penetrates through the at least one substrate. The interconnections structure is disposed over the substrate, and the interconnection structure has a through hole penetrating through the interconnection structure. The through hole, the cavity and the channel are in spatial communication with each other.


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