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For the Inventor, By the Inventor

Yokkaichi, Japan

Yoshiaki Himeno

This inventor holds 12 USPTO granted patents and 2 published patent applications. Top assignee: Kabushiki Kaisha Toshiba. Active years: 2004-2017.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Yoshiaki Himeno. Retrieved from https://idiyas.com/inventor/yoshiaki-himeno

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 12 

% Patents Active = 33.3

Average Co-Inventor Count = 2.6

ph-index = 7

Forward Citations = 127(Granted Patents)


Location History:

  • Yokkaichi, JP (2004 - 2013)
  • Mie-ken, JP (2004 - 2017)

Company Filing History:

goldMedal12 out of 53,262 
 
Kabushiki Kaisha Toshiba
 patents

Years Active: 2004-2017

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12 patents (USPTO):Explore Patents
1. 9589974 - Nonvolatile semiconductor memory device and method for manufacturing same (2017-03-07),
2. 8592978 - Method of fabricating semiconductor device and the semiconductor device (2013-11-26),
3. 7582928 - Nonvolatile semiconductor memory device and its manufacturing method (2009-09-01),
4. 7488646 - Nonvolatile semiconductor memory device and its manufacturing method (2009-02-10),
5. 7382015 - Semiconductor device including an element isolation portion having a recess (2008-06-03),
6. 7166889 - Semiconductor memory device having a gate electrode and a method of manufacturing thereof (2007-01-23),
7. 6987047 - Method of manufacturing a nonvolatile semiconductor memory device having a stacked gate structure (2006-01-17),
8. 6974746 - Method of manufacturing a nonvolatile semiconductor memory device having a stacked gate structure (2005-12-13),
9. 6953962 - Nonvolatile memory device having a gate electrode (2005-10-11),
10. 6869845 - Semiconductor memory device having a memory region and a peripheral region, and a manufacturing method thereof (2005-03-22),
11. 6770932 - Semiconductor memory device having a memory region and a peripheral region, and a manufacturing method thereof (2004-08-03),
12. 6720610 - Nonvolatile semiconductor memory device and its manufacturing method (2004-04-13),

Title: Yoshiaki Himeno: Innovator in Semiconductor Technology

Introduction

Yoshiaki Himeno is a prominent inventor based in Yokkaichi, Japan. He has made significant contributions to the field of semiconductor technology, holding a total of 12 patents. His work focuses on the development of nonvolatile semiconductor memory devices and methods for manufacturing them.

Latest Patents

Among his latest patents is a nonvolatile semiconductor memory device and method for manufacturing the same. This invention includes an interlayer insulating film, an element separating region, and a gate electrode provided on one of the plurality of semiconductor regions in the memory cell region. Additionally, it features a contact electrode that is electrically connected to the semiconductor regions, along with a first and second wiring layer designed to enhance the device's functionality. Another notable patent involves a semiconductor device that comprises a semiconductor substrate and an insulating film, which contains buried wirings arranged at predetermined intervals.

Career Highlights

Yoshiaki Himeno has had a distinguished career at Kabushiki Kaisha Toshiba, where he has been instrumental in advancing semiconductor technologies. His innovative approaches have led to the development of cutting-edge devices that are essential in modern electronics.

Collaborations

Throughout his career, Yoshiaki has collaborated with notable colleagues, including Hiroaki Tsunoda and Tadashi Iguchi. These partnerships have fostered a creative environment that has contributed to the success of their projects.

Conclusion

Yoshiaki Himeno's contributions to semiconductor technology are noteworthy, and his patents reflect his innovative spirit and dedication to advancing the field. His work continues to influence the development of modern electronic devices.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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