Kabushiki Kaisha Toshiba

Yoshiaki Himeno

Hiroaki Tsunoda

Tadashi Iguchi

Takamasa Usui

Jun Iijima

Koichi Matsuno

Hideyuki Kobayashi

Katsuyasu Shiba

Jota Fukuhara

According to one embodiment, a nonvolatile semiconductor memory device includes: an interlayer insulating film; an element separating region separating a semiconductor layer in the memory cell region; a gate electrode provided on one of plurality of semiconductor regions in the memory cell region; a contact electrode having a sidewall in contact with the interlayer insulating film and electrically connected to the one of the plurality of semiconductor regions in the memory cell region; a first wiring layer connected to an upper end of the contact electrode in the memory cell region; and a second wiring layer in a third direction, having an upper end higher than the upper end of the contact electrode, having a lower end lower than the upper end of the contact electrode, and having a sidewall at least partly in contact with the interlayer insulating film in the peripheral region.

Nonvolatile semiconductor memory device and method for manufacturing same

A semiconductor device includes a semiconductor substrate, an insulating film formed above the semiconductor substrate, and a plurality of first buried wirings and a plurality of second buried wirings located in the insulating film at predetermined intervals alternately in a direction parallel to a surface of the semiconductor substrate. Each second buried wiring is formed so that a width between both side surfaces thereof is increased from a lower end toward an upper portion and at an upper surface the width is larger than a width at an upper surface of each first buried wiring.

Method of fabricating semiconductor device and the semiconductor device

A non-volatile semiconductor memory device, which is intended to prevent data destruction by movements of electric charges between floating gates and thereby improve the reliability, includes element isolation/insulation films buried into a silicon substrate to isolate stripe-shaped element-forming regions. Formed on the substrate area floating gate via a first gate insulating film and further a control gate via a second gate insulating film. Source and drain diffusion layers are formed in self-alignment with control gates. The second gate insulating film on the floating gate is divided and separated together with the floating gate by slits above the element isolation/insulation films into discrete portions of individual memory cells.

Nonvolatile semiconductor memory device and its manufacturing method

A non-volatile semiconductor memory device, which is intended to prevent data destruction by movements of electric charges between floating gates and thereby improve the reliability, includes element isolation/insulation films buried into a silicon substrate to isolate stripe-shaped element-forming regions. Formed on the substrate are a floating gate via a first gate insulating film and further a control gate via a second gate insulating film. Source and drain diffusion layers are formed in self-alignment with control gates. The second gate insulating film on the floating gate is divided and separated together with the floating gate by slits above the element isolation/insulation films into discrete portions of individual memory cells.

Semiconductor device including an element isolation portion having a recess

A first aspect of the present invention is providing a non-volatile semiconductor memory device, comprising: a memory cell having a tunnel oxide layer formed on a semiconductor substrate, a floating gate formed on the tunnel oxide layer, a control gate to which voltage is supplied, a source diffusion layer and a drain diffusion layer, the source and drain diffusion layers formed in the semiconductor substrate adjacent to the tunnel oxide layer; a contact layer connected to the drain diffusion layer; and a layer formed above the memory cell, the layer comprising at least one of: 1) a silicon oxide layer to which nitrogen are doped, 2) a silicon oxide layer to which aluminum are doped, 3) an aluminum oxide layer, 4) a silicon oxide layer to which titanium are doped, 5) a silicon oxide layer to which two of nitrogen, aluminum, and titanium are doped, 6) a silicon oxide layer to which nitrogen, aluminum, and titanium are doped, 7) a titanium oxide layer, 8) a titanium and aluminum oxide layer, 9) a simple metal layer comprising one of Ti, Ni, Co, Zr, Cu, Pt, V, Mg, U, Nd, La, and Sc, 10) an alloy layer comprising at least two of Ti, Ni, Co, Zr, Cu, Pt, V, Mg, U, Nd, La, and Sc, and the at least two of Ti, Ni, Co, Zr, Cu, Pt, V, Mg, U, Nd, La, and Sc being included 50% or more, 11) a nitrogenous layer of the alloy layer, and 12) a hydrogenated layer of the alloy layer.

Semiconductor memory device having a gate electrode and a method of manufacturing thereof

Method of manufacturing a nonvolatile semiconductor memory device having a stacked gate structure

A nonvolatile memory device having a gate electrode including: a non volatile memory cell configured to store data, and having a first gate electrode, first and second diffusion layers, the first gate electrode having a first top surface and a first side surface; a peripheral transistor having a second gate electrode, third and fourth diffusion layers, the second gate electrode having a second top surface and a second side surface, and a width between the third and fourth diffusion layers of the second gate electrode being wider than that between the first and second diffusion layers of the first gate electrode; a first contact layer connected to the second top surface of the second gate electrode of the peripheral transistor; and a silicon nitride layer formed above the first side surface of the first gate electrode in the non volatile memory cell and the second side surface of the second gate electrode in the peripheral transistor, the silicon nitride layer not being contact with the first contact layer, a thickness of the silicon nitride layer that is formed above the first and second side surfaces of the first and second gate electrodes being uniform approximately.

Nonvolatile memory device having a gate electrode

A method for manufacturing a semiconductor memory device having a memory region and a peripheral region, including forming a memory cell on the memory region and a peripheral transistor on the peripheral region, the memory cell having a first gate electrode and a first diffusion layer, the peripheral transistor having a second gate electrode and a second diffusion layer; forming a silicon nitride layer above an upper surface and a side surface of the first gate electrode of the memory cell and above an upper surface and a side surface of the second gate electrode of the peripheral transistor; removing the silicon nitride layer that is formed above the upper surface of the second gate electrode of the peripheral transistor; forming an interlayer insulating film above the memory cell and the peripheral transistor; forming a first contact hole that reaches the upper surface of the second gate electrode of the peripheral transistor by removing a portion of the interlayer insulating film; and forming a conductive layer in the first contact hole that is electrically connected to the second gate electrode of the peripheral transistor.

Semiconductor memory device having a memory region and a peripheral region, and a manufacturing method thereof

A semiconductor memory device having a memory region and a peripheral region, comprising: a memory cell configured to store data, the memory cell formed in the memory region of a semiconductor substrate and having a first gate electrode, first and second diffusion layers, the first gate electrode having a first top surface and a first side surface; a peripheral transistor formed in the peripheral region in the semiconductor substrate having a second gate electrode, third and fourth diffusion layers, the second gate electrode having a second top surface and a second side surface; a first contact layer connected to the second top surface of the second gate electrode in the peripheral transistor; and a silicon nitride layer formed above the first side surface of the first gate electrode in the memory cell and the second side surface of the second gate electrode in the peripheral transistor, the silicon nitride layer not being contact with the first contact layer, a thickness of the silicon nitride layer that is formed above the first and second side surfaces of the first and second gate electrodes being unique approximately.

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Yokkaichi, Japan

Yoshiaki Himeno