Yasuyuki Nozuyama

This inventor holds 39 USPTO granted patents, primarily in Semiconductor Design. Top assignees: Kabushiki Kaisha Toshiba, Fujitsu Semiconductor Limited. Active years: 1990-2015.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Yasuyuki Nozuyama. Retrieved from https://idiyas.com/inventor/yasuyuki-nozuyama

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 39

% Patents Active = 61.5

Average Co-Inventor Count = 1.1

ph-index = 11

Forward Citations = 321(Granted Patents)

Location History:

Meguro, JP (1990)
Inashiro, JP (2007 - 2011)
Inagi, JP (2003 - 2012)
Tokyo, JP (1990 - 2015)

Company Filing History:

39 out of 53,276

Kabushiki Kaisha Toshiba

patents

2 out of 1,674

Fujitsu Semiconductor Limited

patents

where one patent can have more than one assignee

Years Active: 1990-2015

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Areas of Expertise:

Semiconductor Integrated Circuit

Fault Coverage

Test Pattern Generation

Delay Fault Testing

Design Verification

Self-Diagnostic Circuit

Test Quality Evaluation

Logic Circuit Testing

Current Reduction Circuit

Linear Feedback Shift Register

Programmable Logic Array

Information Processing System

39 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 9075946 - Method for designing semiconductor integrated circuit (2015-07-07),

2. 8886487 - Bridge fault removal apparatus, bridge fault removal method, and computer readable medium comprising computer program code for removing bridge fault (2014-11-11),

3. 8508249 - Semiconductor integrated circuit and method for designing the same (2013-08-13),

4. 8185863 - Delay fault test quality calculation apparatus, delay fault test quality calculation method, and delay fault test pattern generation apparatus (2012-05-22),

5. 8082534 - Apparatus and method for calculating fault coverage, and fault detection method (2011-12-20),

6. 8051403 - Delay fault test quality calculation apparatus, delay fault test quality calculation method, and delay fault test pattern generation apparatus (2011-11-01),

7. 7966138 - Apparatus for creating test pattern and calculating fault coverage or the like and method for creating test pattern and calculating fault coverage or the like (2011-06-21),

8. 7913143 - Test quality evaluating and improving system for semiconductor integrated circuit and test quality evaluation and improvement method for semiconductor integrated circuit (2011-03-22),

9. 7406645 - Test pattern generating apparatus, method for automatically generating test patterns and computer program product for executing an application for a test pattern generating apparatus (2008-07-29),

10. 7392146 - Fault list and test pattern generating apparatus and method, fault list generating and fault coverage calculating apparatus and method (2008-06-24),

11. 7308660 - Calculation system of fault coverage and calculation method of the same (2007-12-11),

12. 7283918 - Apparatus for analyzing fault of semiconductor integrated circuit, method for the same, and computer readable medium for the same (2007-10-16),

13. 7162674 - Apparatus for selecting test patterns for logic circuit, computer implemented method for selecting test patterns, and computer program product for controlling a computer system so as to select test patterns (2007-01-09),

14. 7139956 - Semiconductor integrated circuit device and test method thereof (2006-11-21),

15. 7096140 - Test system, test method and test program for an integrated circuit by IDDQ testing (2006-08-22),

Title: **Innovative Mind: Yasuyuki Nozuyama and His Contributions to Semiconductor Technology**

Introduction

Yasuyuki Nozuyama is a prominent inventor based in Tokyo, Japan, known for his significant contributions to the field of semiconductor technology. With an impressive portfolio of 39 patents, he has developed numerous innovative solutions that enhance the efficiency and reliability of semiconductor integrated circuits.

Latest Patents

One of Nozuyama's latest inventions is a "Method for Designing Semiconductor Integrated Circuit." This method involves a unique architecture featuring multiple flip-flop groups designed to facilitate serial data transfers. The innovation includes a continuous signal determination circuit that outputs a signal based on the compatibility of the flip-flops within a group, effectively optimizing clock signal provision based on operational needs.

Another significant patent is for a "Bridge Fault Removal Apparatus," which incorporates a bridge fault extraction unit and a test pattern generator aimed at identifying and rectifying bridge faults in semiconductor integrated circuits. This invention reflects Nozuyama’s commitment to improving semiconductor reliability and performance through advanced fault management techniques.

Career Highlights

Yasuyuki Nozuyama has been associated with leading companies in the semiconductor domain, including Toshiba and Fujitsu Semiconductor Limited. His work at these firms has allowed him to collaborate with and learn from some of the best minds in the industry, contributing to his growth as a pioneering inventor.

Collaborations

Throughout his career, Nozuyama has collaborated with notable colleagues such as Akira Nishimura and Atsuo Takatori. These partnerships have been instrumental in fostering innovation and pushing the boundaries of what is possible in semiconductor technology.

Conclusion

Yasuyuki Nozuyama's extensive patent portfolio and collaborative spirit make him a vital figure in the realm of semiconductor innovations. His relentless pursuit of technological advancement continues to influence the industry and inspire future inventors.

Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]