Kabushiki Kaisha Toshiba

Fujitsu Semiconductor Limited

Fujitsu Semicondoctor Limited

Yasuyuki Nozuyama

Akira Nishimura

Atsuo Takatori

Kimiyoshi Usami

Tsuneaki Kudou

Tohru Sasaki

Kazuhiko Ohashi

Misao Miyata

Yukio Sugeno

Mahito Shidou

A semiconductor integrated circuit according to one embodiment includes a plurality of flip-flop groups configured by dividing a plurality of flip-flops, connected in series, for carrying out a serial operation of serially transferring data, a continuous signal determination circuit configured to output a first signal if outputs of the flip-flops contained in the flip-flop group match, and output a second signal in other cases; and a clock gating circuit configured not to provide a clock signal when receiving the first signal and to provide a clock signal when receiving the second signal with respect to the flip-flops other than a head of the flip-flop group.

Method for designing semiconductor integrated circuit

A bridge fault removal apparatus includes a bridge fault extraction unit configured to extract a bridge fault from layout information of a semiconductor integrated circuit, a test pattern generator configured to generate the test pattern aiming at the bridge fault extracted by the bridge fault extraction unit, a logical value information calculator configured to calculate logical value information of all the signals in the semiconductor integrated circuit by applying the test pattern generated by the test pattern generator to logical connection information of the semiconductor integrated circuit, and a bridge fault remover configured to select an exchange signal candidate for an undetected bridge fault signal corresponding to the test pattern based on the logical value information calculated by the logical value information calculator.

Bridge fault removal apparatus, bridge fault removal method, and computer readable medium comprising computer program code for removing bridge fault

Semiconductor integrated circuit and method for designing the same

A delay fault test quality calculation apparatus for calculating delay fault test quality to be achieved by a test pattern to be applied to a semiconductor integrated circuit includes a defect distribution extraction unit, a delay fault-layout element information extraction unit, and a weighting unit. The delay fault test quality calculation apparatus further includes a delay fault test quality calculation unit which calculates the delay fault test quality on the basis of delay design information of the semiconductor integrated circuit, detection information of the test pattern to test the semiconductor integrated circuit, execution conditions of the test, a physical defect distribution extracts the defect distribution extraction unit, and a weights adds the weighting unit.

Delay fault test quality calculation apparatus, delay fault test quality calculation method, and delay fault test pattern generation apparatus

A fault coverage calculating apparatus includes: an extraction module configured to extract information on a pair of wiring lines including a length of the pair adjacent within a predetermined distance range and a distance between the pair and bridge fault information corresponding to the pair from layout information of a semiconductor integrated circuit; a test module configured to perform a determination test for determining whether a bridge fault occurring in the pair is detected by using a bridge fault test pattern of a target; and a calculation module configured to calculate a bridge fault coverage to which the length and the distance are weighted, based on the information on the pair of wiring lines, the bridge fault information, a result of the determination test, and a bridge fault incidence depending on the distance.

Apparatus and method for calculating fault coverage, and fault detection method

The method for creating a test pattern and calculating a fault coverage or the like of the present invention is characterized by creating bridging fault voltage information indicating a voltage of a bridging assumed on the wire derived from an output terminal of a cell, calculating a logical threshold of an input terminal of the cell, extracting bridging fault information on an adjacent wire pair, calculating a detection limit resistance value using the logical threshold, adding the detection limit resistance value to bridging fault voltage information, creating extended bridging fault voltage information, creating a bridging fault list including a bridging fault type based on the extended bridging fault voltage information, creating a test pattern based on the bridging fault list, judging whether or not a bridging fault can be detected through this test pattern, creating fault detection information and calculating a weighted fault coverage based on the fault detection information and bridging fault generation information.

Apparatus for creating test pattern and calculating fault coverage or the like and method for creating test pattern and calculating fault coverage or the like

A test quality evaluating and improving system has a fault-layout information link section which creates a weighted fault dictionary by correlating a layout element related to an undetected fault, out of faults corresponding to a specified fault model and occurring in a circuit to be tested, with the undetected fault as a weight of the undetected fault which cannot be detected by a test pattern for testing the faults; a test quality measure calculating section which multiplies the weight of the undetected fault, the failure mode-fault model correlation factor for correlating the failure mode of the layout element and the fault model, and the failure occurrence rate of each layout element, and outputs an obtained product as a failure remaining rate of the test pattern; a determining section; and a test point inserting section.

Test quality evaluating and improving system for semiconductor integrated circuit and test quality evaluation and improvement method for semiconductor integrated circuit

A test pattern generating apparatus includes an extractor configured to extract a plurality of layout parameters (elements) of a circuit under test based on gate net information and layout information of the circuit, and to link the layout parameters (elements) with corresponding fault models respectively. A weight calculator is configured to calculate a weight for each fault model linked with the layout parameters (elements) for both a plurality of undetected faults of the fault model and a plurality of faults detected by a plurality of test patterns, based on process failure (defect) information and layout parameter (element) information. An automatic test pattern generator is configured to generate the test patterns in accordance with the weight of each fault model linked with the layout parameters (elements).

Test pattern generating apparatus, method for automatically generating test patterns and computer program product for executing an application for a test pattern generating apparatus

The test pattern generating apparatus contains a module configured to generate short information indicative of a relationship between a logical value of an input signal of a cell and a voltage of an electrically shorted portion assumed at an output terminal of the cell; a module configured to calculate a logical threshold value of the input terminal of the cell so as to generate logical threshold value information; a module configured to extract a bridge fault information from layout information of an LSI; a module configured to generate a bridge fault list including a bridge fault type based on the bridge fault information, the short information, and the logical threshold value information; and a module configured to generate a test pattern which detects bridge faults in an adjacent signal wire pair and a bridge fault type.

Fault list and test pattern generating apparatus and method, fault list generating and fault coverage calculating apparatus and method

A calculation system of fault coverage includes a data acquiring module acquiring layout information and gate net data, a layout analysis and fault link module extracting a layout element information and generating a undetected fault list, a fault detecting module generating a detected and undetected fault list, and a weight calculating module adding layout element information as weight, based on a link file between faults and layout element information to be generated based on the layout information, the gate net data, and the detected and undetected fault list.

Calculation system of fault coverage and calculation method of the same

A fault on a measuring point and information about a driving circuit of the fault are extracted. A signal value of a portion related to the fault on the measuring point and an input value of the driving circuit of the portion are obtained when a fault is not included. A fault candidate is extracted from detected faults based on a difference between a measured IDDQ value and a measured estimated IDDQ value when the fault is not included. An estimated calculation value to be a difference of an IDDQ value is calculated between a case when each of the faults is included and a case when the fault is not included. The estimated calculation value is compared with a difference between the measured value and the measured estimation value to decide whether or not the fault candidate is the fault corresponding to a defective portion.

Apparatus for analyzing fault of semiconductor integrated circuit, method for the same, and computer readable medium for the same

An apparatus for selecting test patterns in accordance with an embodiment of the present invention has a first test pattern selecting module configured to define selected test patterns and unselected test patterns, a fault simulation module configured to simulate whether test patterns detect faults, a weighting module configured to add a weight to each of the first undetected faults, a fault sampling module configured to extract second undetected faults from the first undetected faults to which the added weights are given, and a second test pattern selecting module configured to extract additionally selected test patterns based on the added weight.

Apparatus for selecting test patterns for logic circuit, computer implemented method for selecting test patterns, and computer program product for controlling a computer system so as to select test patterns

A semiconductor integrated circuit device includes a test target circuit, a control circuit, and an observation circuit. The control circuit generates a reset signal, and an operation mode signal. The observation circuit is controlled by the signals, and receives input data from observation points in the test target circuit. The observation circuit includes a plurality of flip-flops. The observation circuit performs a reset operation in response to the reset signal. The observation circuit selectively performs a signature-compression operation, and a serial operation of outputting the test result, in response to the operation mode signal. The signature-compression operation is performed, using input data generated in the test target circuit in accordance with test patterns for a normal functional operation.

Semiconductor integrated circuit device and test method thereof

A test system for an integrated circuit includes a grouping module grouping measurement points on basis of values of the quiescent supply current and setting measurement point groups; an average value setting module setting a weighted average value minimizes the sum of dispersion of the quiescent supply current; a calculating module calculating a maximum estimated value of dispersion of the quiescent supply current on the basis of the weighted average value; and a judgment module judging whether the integrated circuit passes or fails the judgment specification.

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Tokyo, Japan

Yasuyuki Nozuyama