logo

For the Inventor, By the Inventor

Saratoga, CA, United States of America

Xiao-Chun Mu

This inventor holds 24 USPTO granted patents and 1 EPO patent, primarily in Polymer Memory Devices. Top assignees: Intel Corporation, Other. Active years: 1990-2006.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Xiao-Chun Mu. Retrieved from https://idiyas.com/inventor/xiao-chun-mu

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 24

% Patents Active = 54.2

 

Average Co-Inventor Count = 2.5

ph-index = 12

Forward Citations = 1,738(Granted Patents)


Location History:

  • Saratoga, CA (US) (1990 - 2006)
  • Saratogo, CA (US) (2003 - 2006)

Company Filing History:

goldMedal23 out of 56,322 
 
Intel Corporation
 patents
silverMedal1 out of 834,513 
Other
 patents

Years Active: 1990-2006

Loading Chart...
Loading Chart...
Areas of Expertise:
Polymer Memory
Adhesion Layer
Stacked Structure
Microelectronic Packaging
Die Protection
Ferroelectric Memory
Interconnect Formation
Flip-Chip Technology
Etching Process
Solder Metallization
Security Devices
CMOS Packaging
24 patents (USPTO):Explore Patents
1. 7078240 - Reliable adhesion layer interface structure for polymer memory electrode and method of making same (2006-07-18),
2. 7018853 - Stepped structure for a multi-rank, stacked polymer memory device and method of making same (2006-03-28),
3. 6964889 - Method to protect an encapsulated die package during back grinding with a solder metallization layer and devices formed thereby (2005-11-15),
4. 6960479 - Stacked ferroelectric memory device and method of making same (2005-11-01),
5. 6952017 - Low-voltage and interface damage-free polymer memory device (2005-10-04),
6. 6902950 - Method to protect an encapsulated die package during back grinding with a solder metallization layer and devices formed thereby (2005-06-07),
7. 6858862 - Discrete polymer memory array and method of making same (2005-02-22),
8. 6798003 - Reliable adhesion layer interface structure for polymer memory electrode and method of making same (2004-09-28),
9. 6756620 - Low-voltage and interface damage-free polymer memory device (2004-06-29),
10. 6624457 - Stepped structure for a multi-rank, stacked polymer memory device and method of making same (2003-09-23),
11. 6600364 - Active interposer technology for high performance CMOS packaging application (2003-07-29),
12. 6586836 - Process for forming microelectronic packages and intermediate structures formed therewith (2003-07-01),
13. 6586822 - Integrated core microelectronic package (2003-07-01),
14. 6524887 - Embedded recess in polymer memory package and method of making same (2003-02-25),
15. 6461954 - Method and an apparatus for forming an under bump metallization structure (2002-10-08),

Title: Innovations by Xiao-Chun Mu: Pioneering Polymer Memory Devices

Introduction

Xiao-Chun Mu, located in Saratoga, California, is a distinguished inventor renowned for his significant contributions to the field of polymer memory devices. Holding an impressive portfolio of 24 patents, Mu has established himself as a key innovator in memory technology, particularly in the development of ferroelectric polymer storage solutions.

Latest Patents

Among Mu's latest patents are notable advancements aimed at enhancing the efficiency and reliability of polymer memory devices. One of his key inventions is titled "Reliable adhesion layer interface structure for polymer memory electrode and method of making same". This patent details a novel polymer memory device comprising two organic adhesion layers that improve the integration of lower and upper electrodes alongside the ferroelectric polymer memory structure. Noteworthy features of this invention include the use of crystalline ferroelectric polymer layers in various compositions and the application of spin-on and Langmuir-Blodgett deposited compositions, enabling compatibility with existing memory systems.

Another significant innovation is titled "Stepped structure for a multi-rank, stacked polymer memory device and method of making same". This invention focuses on a ferroelectric polymer storage device with multiple stacked ferroelectric polymer memory structures, complemented by a pre-fabricated silicon substrate cavity that incorporates interlayer dielectric layers and via structures. This design enhances the data storage capabilities of polymer memory technology, making it suitable for advanced applications.

Career Highlights

Xiao-Chun Mu has had an illustrious career, with a notable stint at Intel Corporation, where he contributed to breakthrough technologies in memory devices. His extensive experience in the sector has enabled him to push the boundaries of polymer memory technology, resulting in numerous patents that are transforming the landscape of data storage solutions.

Collaborations

Throughout his career, Mu has collaborated with several talented individuals, including his colleagues Jian Li and Qing Ma. These collaborations have fostered innovation and have led to the successful development of pioneering memory technologies that hold promise for the future of data storage.

Conclusion

In summary, Xiao-Chun Mu's contributions to polymer memory technology mark him as a significant figure in the field of inventions and innovative solutions. His ongoing dedication to research and development continues to pave the way for advanced memory systems, solidifying his legacy as an impactful inventor in the technology sector.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…