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For the Inventor, By the Inventor

Lancaster, MA, United States of America

William R Halleck

This inventor holds 20 USPTO granted patents and 1 published patent application and 4 EPO patents, primarily in High Speed Interconnects. Top assignees: Intel Corporation, Inter Corporation. Active years: 2008-2024.

IDiyas Innovation Intelligence. (2026). Inventor Profile: William R Halleck. Retrieved from https://idiyas.com/inventor/william-r-halleck

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 20 

% Patents Active = 60.0

 

Average Co-Inventor Count = 4.6

ph-index = 5

Forward Citations = 105(Granted Patents)


Company Filing History:

goldMedal19 out of 56,322 
 
Intel Corporation
 patents
silverMedal1 out of 4 
 
Inter Corporation
 patents

Years Active: 2008-2024

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Areas of Expertise:
Multiple Dies
Hardware Processors
Bimodal PHY
Low Latency
High Speed Interconnect
Link State Transitions
Task Scheduling
DMA Management
Parallel Processing
Data Transfers
Frame Handling
Context Cache
20 patents (USPTO):Explore Patents
1. 11899615 - Multiple dies hardware processors and methods (2024-02-13),
2. 11586579 - Multiple dies hardware processors and methods (2023-02-21),
3. 11354264 - Bimodal PHY for low latency in high speed interconnects (2022-06-07),
4. 11294852 - Multiple dies hardware processors and methods (2022-04-05),
5. 10963415 - Bimodal PHY for low latency in high speed interconnects (2021-03-30),
6. 10931329 - High speed interconnect with channel extension (2021-02-23),
7. 10795853 - Multiple dies hardware processors and methods (2020-10-06),
8. 10599602 - Bimodal phy for low latency in high speed interconnects (2020-03-24),
9. 10372657 - Bimodal PHY for low latency in high speed interconnects (2019-08-06),
10. 10324882 - High performance interconnect link state transitions (2019-06-18),
11. 10152446 - Link-physical layer interface adapter (2018-12-11),
12. 10025746 - High performance interconnect (2018-07-17),
13. 9910809 - High performance interconnect link state transitions (2018-03-06),
14. 8135869 - Task scheduling to devices with same connection address (2012-03-13),
15. 7797463 - Hardware assisted receive channel frame handling via data offset comparison in SAS SSP wide port applications (2010-09-14),

Title: Innovator Spotlight: William R Halleck - Revolutionizing Hardware Processors

Introduction:

William R Halleck, a prolific inventor based in Lancaster, MA (US), has left an indelible mark on the tech industry with his groundbreaking innovations. With an impressive portfolio of 20 patents under his belt, Halleck is recognized for his contributions to the field of hardware processors.

Latest Patents:

Among his recent patents is the cutting-edge invention titled "Multiple Dies Hardware Processors and Methods," which explores advancements in hardware processors featuring multiple interconnected dies. This technology showcases a hardware processor comprising physically separate dies and an interconnect to seamlessly link these dies together, underscoring Halleck's expertise in optimizing processor performance.

Career Highlights:

Halleck's distinguished career includes tenure at renowned companies such as Intel Corporation and Inter Corporation, where he sharpened his skills and honed his craft. His innovative spirit and dedication to excellence have been instrumental in shaping the landscape of modern technology.

Collaborations:

Throughout his career, Halleck has collaborated with esteemed professionals in the industry, including Venkatraman Iyer and Rahul R Shah. These synergistic partnerships have fostered creativity and propelled the development of cutting-edge technologies, solidifying Halleck's reputation as a visionary inventor.

Conclusion:

In conclusion, William R Halleck stands as a trailblazing inventor whose ingenuity has redefined the possibilities within the realm of hardware processors. His relentless pursuit of innovation and his commitment to pushing the boundaries of technology continue to inspire the next generation of inventors and innovators worldwide.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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