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San Jose, CA, United States of America

William Jeffrey Schaefer

USPTO Granted Patents = 8

Average Co-Inventor Count = 2.5

ph-index = 7

Forward Citations = 353(Granted Patents)

Location History:

Dublin, CA (US) (2005)
San Jose, CA (US) (2000 - 2007)

Company Filing History:

National Semiconductor Corporation

Years Active: 2000-2007

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8 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 7287323 - Materials and structure for a high reliability BGA connection between LTCC and PB boards (2007-10-30),

2. RE38789 - Semiconductor wafer having a bottom surface protective coating (2005-09-05),

3. 6800815 - Materials and structure for a high reliability bga connection between LTCC and PB boards (2004-10-05),

4. 6770513 - Thermally enhanced flip chip packaging arrangement (2004-08-03),

5. 6175162 - Semiconductor wafer having a bottom surface protective coating (2001-01-16),

6. 6084308 - Chip-on-chip integrated circuit package and method for making the same (2000-07-04),

7. 6075290 - Surface mount die: wafer level chip-scale package and process for making (2000-06-13),

8. 6023094 - Semiconductor wafer having a bottom surface protective coating (2000-02-08),

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