National Semiconductor Corporation

William Jeffrey Schaefer

Nikhil Vishwanath Kelkar

Pai-Hsiang Kao

Michael Richard Ehlert

Seshadri Vikram

John A Jackson

A ceramic circuit structure comprising a plurality of ceramic layers and at least one electronic component embedded within the plurality of ceramic layers. Within a first one of the ceramic layers is a via that passes through the ceramic layer. A contact pad is formed on a surface of the ceramic layer. A barrier cap is formed between the via and the contact pad. A dielectric ring covers a peripheral portion of the contact pad and an adjacent portion of the dielectric material layer surface immediately surrounding the contact pad, such that any solder that is applied to the contact does not contact the peripheral portion of the contact pad or the ceramic material.

Materials and structure for a high reliability BGA connection between LTCC and PB boards

Disclosed is a packaged integrated circuit device. The device includes a die having a plurality of electrical contacts on a first surface of the die and a protective film adhered directly to a back surface of the die, the protective film being thick enough to allow laser marking of the protective film without the laser penetrating to the die. In one preferred embodiment, the protective film of the device is a thick film formed by screen printing. In a preferred embodiment, the protective film has a thickness of between about 1.5 and 5 mils. Also, disclosed is a method of fabricating a semiconductor wafer having a wafer substrate with a top surface and a bottom surface and a plurality of dies. In this embodiment, the method includes providing a plurality of dies on the top surface of the wafer substrate, applying a thick film over the bottom surface of the wafer substrate, adhering the thick film to a mounting tape that is not ultraviolet curable, and dicing the wafer to separate the dies. The thick film reduces chipping along edges of the separated dies.

Semiconductor wafer having a bottom surface protective coating

Materials and structure for a high reliability bga connection between LTCC and PB boards

An improved arrangement for attaching a heat sink to a flip chip type die is disclosed. More specifically, the heat sink is attached to the back surface of the flip chip die by a metallic solder material. Such an arrangement provides a good thermal conductivity between the die and the heat sink. In some embodiments, the die is mounted on a grid array type substrate in a flip chip arrangement such that the die contacts are coupled to adjacent I/O pads on the substrate. In another aspect, one or more metallic intermediate die attach layers are deposited over the back surface of the die to form a solderable die surface. The heat sink is then attached to the solderable die surface. This approach works well when the chosen solder does not adhere well to the semiconductor die material. In one preferred implementation the intermediate metallic layers include a barrier layer that is deposited over the back surface of the die and a solderable metallic layer that is deposited over the barrier layer. In a method aspect, the barrier and metallic layers may be deposited on the back side of a wafer during fabrication which provides the desired structure after dicing.

Thermally enhanced flip chip packaging arrangement

A chip-on-chip integrated circuit package is disclosed. The device includes a substrate having a plurality of conductive landings disposed on a first surface thereof, a first die that is positioned over a substrate, and a second die that is mounted on the first die. The first die has a plurality of I/O pads that face away from the substrate. The second die includes a first set of contacts that mate with the conductive landings on the substrate and a second set of contacts that mate with the I/O pads on the first die. In a preferred embodiment, the first set of contacts on the second die take the form of a first set of solder bumps, and the second set of contacts on the second die take the form of a second set of solder bumps. The device may also include a die attach material for attaching the first die to the substrate, wherein the die attach material and the first and second sets of solder bumps have a configuration that facilitates bonding and at least a portion of each of the solder bumps in the first and second sets of solder bumps and the die attach material have a substantially common reflow temperature. A method for making a chip-on-chip integrated circuit package is also disclosed.

Chip-on-chip integrated circuit package and method for making the same

Disclosed is an IC package. The IC package includes a die having a plurality of conductive pads. A passivation layer is formed over the conductive pads such that the passivation layer has a plurality of passivation vias. Each passivation via is positioned over an associated one of the conductive pads. A resilient protective layer is formed over the passivation layer. The resilient protective layer has a plurality of resilient vias, wherein each resilient via is associated with an associated passivation via. A plurality of under bump pads are in electrical contact with the conductive pads, and each under bump pad is associated with one of the resilient vias. A plurality of contact bumps are formed over the plurality of under bump pads such that each one of the contact bumps is electrically coupled with a selected one of the under bump pads and such that each contact bump is electrically coupled with a selected one of the conductive pads. The resilient protective layer is arranged to absorb stresses introduced at the contact bumps when the IC package is attached to an external substrate; the contact bumps are formed from a material that facilitates absorption of stresses by the resilient protective layer, and the resilient protective layer is further arranged to protect the die. In one preferred embodiment, each under bump pad includes a lip that extends over a portion of the resilient layer. In another preferred embodiment, the contact bumps are formed from a eutectic tin-lead alloy. In another embodiment, a circuit board is disclosed. The circuit board includes a substrate having a plurality of board contacts and the IC package as recited above. In this embodiment, the IC package is attached to the substrate such that each of the contact bumps is coupled with an associated one of the board contacts. In a preferred embodiment, the resilient protective layer of the IC package absorbs stresses introduced at the contact bumps such that an underfill layer is not required between the IC package and the substrate.

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San Jose, CA, United States of America

William Jeffrey Schaefer