William Clark Naylor, Jr

This inventor holds 6 USPTO granted patents. Top assignee: Synopsys, Inc.. Active years: 2005-2020.

IDiyas Innovation Intelligence. (2026). Inventor Profile: William Clark Naylor, Jr. Retrieved from https://idiyas.com/inventor/william-clark-naylor-jr

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 6

% Patents Active = 100.0

Average Co-Inventor Count = 2.3

ph-index = 3

Forward Citations = 20(Granted Patents)

Company Filing History:

6 out of 2,604

Synopsys, Inc.

patents

Years Active: 2005-2020

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6 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 10650109 - Boolean satisfiability (SAT) solver (2020-05-12),

2. 10346578 - Placement-based congestion-aware logic restructuring (2019-07-09),

3. 10331834 - Optimizing the ordering of the inputs to large commutative-associative trees of logic gates (2019-06-25),

4. 8146047 - Automation method and system for assessing timing based on gaussian slack (2012-03-27),

5. 7484194 - Automation method and system for assessing timing based on Gaussian slack (2009-01-27),

6. 6951003 - Placing cells of an IC design using partition preconditioning (2005-09-27),

Title: William Clark Naylor, Jr: Innovator in Boolean Satisfiability and Integrated Circuit Design

Introduction

William Clark Naylor, Jr. is a prominent inventor based in San Jose, CA. He has made significant contributions to the fields of Boolean satisfiability and integrated circuit design. With a total of 6 patents to his name, Naylor has demonstrated a strong commitment to advancing technology through innovative solutions.

Latest Patents

Naylor's latest patents include groundbreaking techniques and systems for solving Boolean satisfiability (SAT) problems. These embodiments generate an extended resolution proof, effectively addressing many technological challenges that can be modeled as SAT problems. By solving the underlying SAT problem, these innovations can resolve the original technological issues. Another notable patent focuses on placement-based congestion-aware logic restructuring. This patent describes systems and techniques for optimizing integrated circuit (IC) designs. The process involves creating a Wire-Length-Area Model (WLAM) for a portion of a circuit design, transforming it into a logically-equivalent design, and ultimately achieving an optimized placed-and-routed circuit.

Career Highlights

Naylor is currently employed at Synopsys, Inc., where he continues to push the boundaries of technology. His work has been instrumental in developing solutions that enhance the efficiency and effectiveness of integrated circuits. His innovative approach has garnered attention in the tech community.

Collaborations

Some of Naylor's notable coworkers include Brent L Gregory and Bogdan Craciun. Their collaborative efforts contribute to the advancement of technology in their respective fields.

Conclusion

William Clark Naylor, Jr. is a distinguished inventor whose work in Boolean satisfiability and integrated circuit design has made a significant impact. His innovative patents and contributions to Synopsys, Inc. highlight his dedication to solving complex technological problems.

Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]