Synopsys, Inc.

William Clark Naylor, Jr

Brent L Gregory

Bogdan Craciun

Ross Alexander Donelly

Jagat B Patel

Jaime Wong

Troy W Barbee, Iii

Techniques and systems for solving a Boolean satisfiability (SAT) problem are described. Specifically, embodiments solve the SAT problem by generating an extended resolution proof. It is well-known that many technological problems can be modeled as SAT problems, and that solving an underlying SAT problem effectively solves the original technological problem. Therefore, embodiments described herein can be used to solve any technological problem that can be modeled as a SAT problem.

Boolean satisfiability (SAT) solver

Systems and techniques for optimizing an integrated circuit (IC) design are described. Some embodiments can transform a circuit design into a logically-equivalent circuit design by: (1) creating a Wire-Length-Area Model (WLAM) for a portion of a first circuit design, (2) creating a second circuit design by replacing the portion of the first circuit design by the WLAM, (3) placing and routing the second circuit design to obtain a placed-and-routed second circuit design, and (4) creating a third circuit design that is logically-equivalent to the first circuit design based on the placed-and-routed second circuit design.

Placement-based congestion-aware logic restructuring

A method of optimizing a netlist for a circuit comprising identifying a logic tree with a single output and a plurality of interchangeable inputs, and calculate the optimal permutation of the plurality of inputs. The method further comprising modify the netlist based on the optimal permutation, and optimizing the modified netlist.

Optimizing the ordering of the inputs to large commutative-associative trees of logic gates

An automated design process using a computer system includes identifying a set of timing endpoints in a circuit defined by a machine-readable file. Values of slack in the estimated arrival times for the timing endpoints are assigned. Probability distribution functions, such as Gaussian distributions, are assigned for the respective values of slack, and are combined. The combination of probability distribution functions represents a measure of circuit performance. The measure is computed for alternative implementations of the circuit, and used to identify an alternative more likely to meet timing constraints.

Automation method and system for assessing timing based on gaussian slack

Automation method and system for assessing timing based on Gaussian slack

A method and system of placing cells of an IC design using partition preconditioning. In one embodiment, cells of an integrated circuit design are grouped to model curvature of an objective function. The grouping produce a plurality of cell clusters. The model formed may be a binary tree. The curvature of the objective function for each of the cell clusters is estimated. Interactions between said cell clusters are described as a relation. A set of preconditioning values which achieves a separation of variables of the relation is determined. The preconditioning may be applied to a conjugate gradient placement process to advantageously decrease the number of iterations required to produce an optimized placement of the cells.

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San Jose, CA, United States of America

William Clark Naylor, Jr