Hsinchu, Taiwan

Wen-Koi Lai

USPTO Granted Patents = 5 

Average Co-Inventor Count = 6.8

ph-index = 1

Forward Citations = 11(Granted Patents)


Company Filing History:


Years Active: 2001-2025

Loading Chart...
5 patents (USPTO):

Title: The Innovations of Wen-Koi Lai

Introduction

Wen-Koi Lai is a notable inventor based in Hsinchu, Taiwan. He has made significant contributions to the field of integrated circuit design, holding a total of five patents. His work focuses on improving the efficiency and compliance of integrated circuit layout generation methods.

Latest Patents

Wen-Koi Lai's latest patents include innovative methods for generating integrated circuit (IC) layout diagrams. One method involves receiving an IC layout diagram that includes a gate region and a gate via. The gate via is positioned within an active region and along the width of the gate region. The process includes receiving a first gate resistance value, retrieving a second gate resistance value from a reference, and using both values to determine compliance with design specifications. If the layout does not comply, modifications are made to ensure it meets the required standards. Another similar patent outlines a method that also focuses on determining gate resistance values and modifying the IC layout diagram based on compliance with design specifications.

Career Highlights

Wen-Koi Lai has worked with prominent organizations such as Taiwan Semiconductor Manufacturing Company and the National Science Council. His experience in these institutions has allowed him to refine his skills and contribute to advancements in semiconductor technology.

Collaborations

Wen-Koi Lai has collaborated with notable colleagues, including Ke-Ying Su and Jon-Hsu Ho. These partnerships have fostered a collaborative environment that encourages innovation and the sharing of ideas.

Conclusion

Wen-Koi Lai's contributions to integrated circuit design through his patents and collaborations highlight his importance in the field of technology. His innovative methods continue to influence the development of efficient IC layout generation techniques.

This text is generated by artificial intelligence and may not be accurate.
Please report any incorrect information to support@idiyas.com
Loading…