The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 15, 2025
Filed:
Jan. 24, 2024
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Ke-Ying Su, Hsinchu, TW;
Jon-Hsu Ho, Hsinchu, TW;
Ke-Wei Su, Hsinchu, TW;
Liang-Yi Chen, Hsinchu, TW;
Wen-Hsing Hsieh, Hsinchu, TW;
Wen-Koi Lai, Hsinchu, TW;
Keng-Hua Kuo, Hsinchu, TW;
KuoPei Lu, Hsinchu, TW;
Lester Chang, Hsinchu, TW;
Ze-Ming Wu, Hsinchu, TW;
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;
Abstract
A method of generating an IC layout diagram includes receiving an IC layout diagram including a gate region and a gate via, the gate via being positioned at a location within an active region and along a width of the gate region extending across the active region, receiving a first gate resistance value of the gate region, retrieving a second gate resistance value from a resistance value reference based on the location and the width, using the first and second resistance values to determine that the IC layout diagram does not comply with a design specification, and based on the non-compliance with the design specification, modifying the IC layout diagram.