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For the Inventor, By the Inventor

San Jose, CA, United States of America

Weidan Li

USPTO Granted Patents = 14 


Average Co-Inventor Count = 3.6

ph-index = 7

Forward Citations = 268(Granted Patents)


Company Filing History:

goldMedal12 out of 3,715 
 
Lsi Logic Corporation
 patents
silverMedal1 out of 1,901 
 
Marvellworld Trade Ltd.
 patents
bronzeMedal1 out of 5,162 
 
Marvell International Limited
 patents

Years Active: 2001-2015

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14 patents (USPTO):Explore Patents
1. 8946890 - Power/ground layout for chips (2015-02-03),
2. 8921938 - Laterally diffused metal oxide semiconductor (LDMOS) device with overlapping wells (2014-12-30),
3. 7321254 - On-chip automatic process variation, supply voltage variation, and temperature deviation (PVT) compensation method (2008-01-22),
4. 7181712 - Method of optimizing critical path delay in an integrated circuit design (2007-02-20),
5. 7000163 - Optimized buffering for JTAG boundary scan nets (2006-02-14),
6. 6893962 - Low via resistance system (2005-05-17),
7. 6807656 - Decoupling capacitance estimation and insertion flow for ASIC designs (2004-10-19),
8. 6794756 - Integrated circuit structure having low dielectric constant material and having silicon oxynitride caps over closely spaced apart metal lines (2004-09-21),
9. 6756674 - Low dielectric constant silicon oxide-based dielectric layer for integrated circuit structures having improved compatibility with via filler materials, and method of making same (2004-06-29),
10. 6608365 - Low leakage PMOS on-chip decoupling capacitor cells compatible with standard CMOS cells (2003-08-19),
11. 6569751 - Low via resistance system (2003-05-27),
12. 6423628 - Method of forming integrated circuit structure having low dielectric constant material and having silicon oxynitride caps over closely spaced apart metal lines (2002-07-23),
13. 6391768 - Process for CMP removal of excess trench or via filler metal which inhibits formation of concave regions on oxide surface of integrated circuit structure (2002-05-21),
14. 6329720 - Tungsten local interconnect for silicon integrated circuit structures, and method of making same (2001-12-11),

Title: Weidan Li: Innovator in Semiconductor Technology

Introduction

Weidan Li is a prominent inventor based in San Jose, California, known for his significant contributions to semiconductor technology. With a total of 14 patents to his name, Li has made remarkable advancements in the design and functionality of chips.

Latest Patents

Among his latest patents is a design for a power/ground layout for chips. This innovation involves a chip that comprises a base metal layer formed over a first semiconductor die, along with a first metal layer that includes a plurality of islands configured to route either a ground signal or a power signal. Additionally, the chip features a second metal layer that also includes islands for routing these signals. Another notable patent is for a laterally diffused metal oxide semiconductor (LDMOS) device with overlapping wells. This design includes a transistor with a p-type well and an n-type well, where parts of these wells overlap, enhancing the device's performance.

Career Highlights

Weidan Li has worked with several notable companies throughout his career, including LSI Logic Corporation and Marvell Technology Group Ltd. His experience in these organizations has allowed him to refine his skills and contribute to cutting-edge technologies in the semiconductor field.

Collaborations

Li has collaborated with talented individuals such as Benjamin Mbouombouo and Wilbur G. Catabay. These partnerships have fostered innovation and creativity in his projects.

Conclusion

Weidan Li's work in semiconductor technology exemplifies the spirit of innovation and dedication to advancing the field. His patents and collaborations continue to influence the industry and inspire future inventors.

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