The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 03, 2015

Filed:

Oct. 19, 2011
Applicants:

Sehat Sutardja, Los Altos Hills, CA (US);

Chung Chyung Han, San Jose, CA (US);

Weidan LI, San Jose, CA (US);

Shuhua Yu, San Jose, CA (US);

Chuan-cheng Cheng, Fremont, CA (US);

Albert Wu, Palo Alto, CA (US);

Inventors:

Sehat Sutardja, Los Altos Hills, CA (US);

Chung Chyung Han, San Jose, CA (US);

Weidan Li, San Jose, CA (US);

Shuhua Yu, San Jose, CA (US);

Chuan-Cheng Cheng, Fremont, CA (US);

Albert Wu, Palo Alto, CA (US);

Assignee:

Marvell World Trade Ltd., St. Michael, BB;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); H01L 23/00 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 25/065 (2006.01); H01L 25/00 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 24/06 (2013.01); H01L 23/5226 (2013.01); H01L 23/5286 (2013.01); H01L 24/73 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01); H01L 23/3107 (2013.01); H01L 24/05 (2013.01); H01L 24/16 (2013.01); H01L 24/45 (2013.01); H01L 24/48 (2013.01); H01L 25/0655 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/061 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/45111 (2013.01); H01L 2224/45116 (2013.01); H01L 2224/45124 (2013.01); H01L 2224/45139 (2013.01); H01L 2224/45144 (2013.01); H01L 2224/45147 (2013.01); H01L 2224/48247 (2013.01); H01L 2224/731 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06527 (2013.01); H01L 2924/01013 (2013.01); H01L 2924/01014 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/01032 (2013.01); H01L 2924/01079 (2013.01); H01L 2924/01082 (2013.01); H01L 2924/014 (2013.01); H01L 2924/10252 (2013.01); H01L 2924/10253 (2013.01); H01L 2924/10271 (2013.01); H01L 2924/10329 (2013.01); H01L 2924/14 (2013.01); H01L 2924/30107 (2013.01); H01L 2924/01005 (2013.01); H01L 2924/01006 (2013.01); H01L 2924/01019 (2013.01); H01L 2924/01033 (2013.01); H01L 2924/01047 (2013.01); H01L 2924/0105 (2013.01); H01L 2224/05624 (2013.01); H01L 2224/05647 (2013.01); H01L 2224/48624 (2013.01); H01L 2224/48647 (2013.01); H01L 2224/48824 (2013.01); H01L 2224/48847 (2013.01); H01L 2224/48724 (2013.01); H01L 2224/48747 (2013.01); H01L 2924/01028 (2013.01);
Abstract

Embodiments of the present disclosure provide a chip that comprises a base metal layer formed over a first semiconductor die and a first metal layer formed over the base metal layer. The first metal layer includes a plurality of islands configured to route at least one of (i) a ground signal or (ii) a power signal in the chip. The chip further comprises a second metal layer formed over the first metal layer. The second metal layer includes a plurality of islands configured to route at least one of (i) the ground signal or (ii) the power signal in the chip.


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