Hsinchu, Taiwan

Wei Tse Hsu

This inventor holds 2 USPTO granted patents and 7 published patent applications. Top assignee: Taiwan Semiconductor Manufacturing Comp. Ltd.. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Wei Tse Hsu. Retrieved from https://idiyas.com/inventor/wei-tse-hsu-1rwmsz5p

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 2 

% Patents Active = 100.0

Average Co-Inventor Count = 3.0

ph-index = 1


Company Filing History:


Years Active: 2026

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2 patents (USPTO):Explore Patents

Title: Wei Tse Hsu - Innovator in Semiconductor Technology

Introduction

Wei Tse Hsu is an inventor based in Zhubei, Taiwan. He is known for his contributions to semiconductor technology, particularly in the area of substrate thinning. Although he currently holds no granted patents, his innovative ideas are reflected in his latest patent applications.

Latest Patent Applications

Wei Tse Hsu's latest patent application is titled "Etch Stop Region for Semiconductor Device Substrate Thinning." This method involves implanting impurities in a semiconductor substrate to create an etch stop region within the substrate. The process includes forming a transistor structure on the front side of the semiconductor substrate and a front-side interconnect structure over the transistor. A thinning process is then performed on the back side of the substrate to reduce its thickness, with the etch stop region slowing down this thinning process. Finally, a back-side interconnect structure is formed over the back side of the semiconductor substrate.

Conclusion

Wei Tse Hsu is an emerging inventor in the field of semiconductor technology, with innovative applications that could significantly impact the industry. His work demonstrates a commitment to advancing semiconductor device design and functionality.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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