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For the Inventor, By the Inventor

Portland, OR, United States of America

Vishal Khandelwal

This inventor holds 8 USPTO granted patents and 1 published patent application and 1 EPO patent. Top assignee: Synopsys, Inc.. Active years: 2010-2024.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Vishal Khandelwal. Retrieved from https://idiyas.com/inventor/vishal-khandelwal

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 8 

% Patents Active = 100.0

 

Average Co-Inventor Count = 3.6

ph-index = 3

Forward Citations = 39(Granted Patents)


Location History:

  • Hillsboro, OR (US) (2010 - 2023)
  • Portland, OR (US) (2014 - 2023)

Company Filing History:

goldMedal8 out of 2,595 
 
Synopsys, Inc.
 patents

Years Active: 2010-2024

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8 patents (USPTO):Explore Patents
1. 12124782 - Machine learning-enabled estimation of path-based timing analysis based on graph-based timing analysis (2024-10-22),
2. 11836641 - Machine learning-based prediction of metrics at early-stage circuit design (2023-12-05),
3. 11741282 - Reinforcement learning-based adjustment of digital circuits (2023-08-29),
4. 11636388 - Machine learning-based algorithm to accurately predict detail-route DRVS for efficient design closure at advanced technology nodes (2023-04-25),
5. 11256845 - Machine-learning driven prediction in integrated circuit design (2022-02-22),
6. 9245075 - Concurrent optimization of timing, area, and leakage power (2016-01-26),
7. 8924901 - Look-up based fast logic synthesis (2014-12-30),
8. 7853915 - Interconnect-driven physical synthesis using persistent virtual routing (2010-12-14),
Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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