Vishal Khandelwal

This inventor holds 8 USPTO granted patents and 1 published patent application and 1 EPO patent. Top assignee: Synopsys, Inc.. Active years: 2010-2024.

USPTO Granted Patents = 8 (Patent Applications = 1)

% Patents Active = 100.0

EPO Patents = 1 (Patent Applications = 2)

Average Co-Inventor Count = 3.6

ph-index = 3

Forward Citations = 39(Granted Patents)

Location History:

Hillsboro, OR (US) (2010 - 2023)
Portland, OR (US) (2014 - 2023)

Company Filing History:

8 out of 2,595

Synopsys, Inc.

patents

Years Active: 2010-2024

Loading Chart...

8 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 12124782 - Machine learning-enabled estimation of path-based timing analysis based on graph-based timing analysis (2024-10-22),

2. 11836641 - Machine learning-based prediction of metrics at early-stage circuit design (2023-12-05),

3. 11741282 - Reinforcement learning-based adjustment of digital circuits (2023-08-29),

4. 11636388 - Machine learning-based algorithm to accurately predict detail-route DRVS for efficient design closure at advanced technology nodes (2023-04-25),

5. 11256845 - Machine-learning driven prediction in integrated circuit design (2022-02-22),

6. 9245075 - Concurrent optimization of timing, area, and leakage power (2016-01-26),

7. 8924901 - Look-up based fast logic synthesis (2014-12-30),

8. 7853915 - Interconnect-driven physical synthesis using persistent virtual routing (2010-12-14),

Profile summary based on public USPTO records.

Please report any incorrect information to [email protected]

1 patent pending:

Please report any incorrect information to [email protected]

1 patent (EPO):

Please report any incorrect information to [email protected]

2 patents pending (EPO):

Please report any incorrect information to [email protected]