Vishal Khandelwal

Title: Vishal Khandelwal: Inventor in Machine Learning and Circuit Design.

Introduction

Vishal Khandelwal is an inventor based in Portland, Oregon, whose patent work focuses on applying machine learning to electronic circuit design and timing analysis. He is associated with Synopsys, Inc. His portfolio includes 8 patents.

Latest Patents

Khandelwal’s recent patent work addresses ways to use machine learning to improve circuit-design analysis and decision-making.

“Machine learning-enabled estimation of path-based timing analysis based on graph-based timing analysis” describes applying graph-based timing analysis to a routed gate-level netlist, then using a machine-learning model to refine the resulting timing estimates. The model can be trained with path-based timing analysis results as ground truth, helping make graph-based estimates more accurate.

“Machine learning-based prediction of metrics at early-stage circuit design” focuses on predicting whether a circuit is likely to meet design constraints before the design is complete. The approach uses features from partial circuit designs, such as designs at the synthesis or placement stage, to estimate outcomes and rank candidate designs for further development.

Career Highlights

Khandelwal’s disclosed inventions connect machine learning with practical challenges in integrated-circuit design. They aim to help designers assess timing and constraint performance earlier, when less information is available and completing a full design may be costly.

Collaborations

His listed coworkers include Siddhartha Nath and Sanjay Dhar. His work is associated with Synopsys, Inc., a company active in electronic design automation and semiconductor design tools.

Conclusion

Vishal Khandelwal’s patent portfolio highlights machine-learning methods for improving timing estimates and evaluating circuit designs earlier in the design process.