The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 25, 2023

Filed:

Feb. 04, 2020
Applicant:

Synopsys, Inc., Mountain View, CA (US);

Inventors:

Wei-Ting Chan, Hillsboro, OR (US);

Siddhartha Nath, Mountain View, CA (US);

Vishal Khandelwal, Hillsboro, OR (US);

Assignee:

Synopsys, Inc., Mountain View, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06N 20/00 (2019.01); G06F 30/398 (2020.01); G06F 30/323 (2020.01); G06F 30/3953 (2020.01); G06F 30/327 (2020.01); G06F 30/3947 (2020.01);
U.S. Cl.
CPC ...
G06N 20/00 (2019.01); G06F 30/323 (2020.01); G06F 30/327 (2020.01); G06F 30/398 (2020.01); G06F 30/3947 (2020.01); G06F 30/3953 (2020.01);
Abstract

A machine learning (ML) system is trained to predict the number of design rules violations of a circuit design that includes a multitude of Gcells. To achieve this, a netlist associated with the circuit design is placed by a place and route tool. A first list of features associated with the placed netlist is delivered to the ML system. A global route of the circuit design is performed by a global router. Next, a second list of features is delivered from the global router to the ML system. Thereafter, a detailed route of the circuit design is performed by a detailed router. A label associated with each Gcell in the circuit design is delivered to the ML system from the detailed route. The ML system is trained using the first and second list of features and the labels.


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