Chennai, India

Venkatesh Mohanakrishnaswamy

This inventor holds 9 USPTO granted patents and 1 published patent application. Top assignees: Stmicroelectronics Gmbh, Stmicroelectronics Asia Pacific Pte Limited. Active years: 2011-2014.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Venkatesh Mohanakrishnaswamy. Retrieved from https://idiyas.com/inventor/venkatesh-mohanakrishnaswamy

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 9 

% Patents Active = 100.0

Average Co-Inventor Count = 2.7

ph-index = 2

Forward Citations = 6(Granted Patents)


Location History:

  • Coppell, TX (US) (2011 - 2014)
  • Chennai, IN (2012 - 2014)
  • Tamil Nadu, IN (2013 - 2014)

Company Filing History:


Years Active: 2011-2014

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9 patents (USPTO):Explore Patents

Title: Venkatesh Mohanakrishnaswamy: Innovator in Microelectromechanical Systems

Introduction

Venkatesh Mohanakrishnaswamy is a prominent inventor based in Chennai, India. He has made significant contributions to the field of microelectromechanical systems (MEMS) and holds a total of 9 patents. His work focuses on advancing semiconductor technology and enhancing the functionality of MEMS devices.

Latest Patents

One of his latest patents is for an embedded MEMS semiconductor substrate and related method of forming. This innovation presents a starting material for subsequent semiconductor device processing. The MEMS device is formed in a semiconductor substrate, which includes at least one MEMS electrode and a buried silicon dioxide sacrificial layer for releasing the MEMS. A planarizing layer is applied over the substrate, MEMS device, and MEMS electrode, followed by a polysilicon protection layer. A silicon nitride capping layer is then applied over the polysilicon protection layer, and a polysilicon seed layer is placed over the silicon nitride capping layer. The MEMS device is released by removing a portion of the buried silicon dioxide sacrificial layer, allowing for an epitaxial layer to be grown over the polysilicon seed layer for subsequent semiconductor wafer processing.

Another notable patent involves a method of forming a die that has an integrated circuit (IC) region adjacent to a MEMS region. This method includes forming a first layer with a specific dopant concentration, which contains both an integrated circuit region and a micro-electromechanical region. The micro-electromechanical region is then doped to achieve a different dopant concentration. A second layer is formed over the first layer, and the micro-electromechanical region is further doped. This innovative approach allows for the formation of a micro-electromechanical structure and active components in the integrated circuit region.

Career Highlights

Venkatesh has worked with notable companies in the semiconductor industry, including STMicroelectronics GmbH and STMicroelectronics Asia Pacific Pte Limited. His experience in these organizations has contributed to his expertise in MEMS and semiconductor technologies.

Collaborations

Throughout his career, Venkatesh has collaborated with talented professionals, including Loi Ngoc Nguyen and Olivier Le Neel. These collaborations have further enriched his work and innovations in the field.

Conclusion

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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