Company Filing History:

12 out of 2,546

Cadence Design Systems, Inc.

International Business Machines Corporation

patents

Years Active: 2011-2019

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14 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 10510774 - Integrated circuit power distribution network (2019-12-17),

2. 10192018 - Method and system for implementing efficient trim data representation for an electronic design (2019-01-29),

3. 9767245 - Method, system, and computer program product for improving mask designs and manufacturability of electronic designs for multi-exposure lithography (2017-09-19),

4. 9286432 - Methods, systems, and articles of manufacture for implementing correct-by-construction physical designs with multiple-patterning-awareness (2016-03-15),

5. 9245076 - Orthogonal circuit element routing (2016-01-26),

6. 9087174 - Methods, systems, and articles of manufacture for implementing multiple-patterning-aware design rule check for electronic designs (2015-07-21),

7. 8863048 - Methods, systems, and articles of manufacture for implementing multiple-patterning-aware correct-by-construction layout processing for an electronic design (2014-10-14),

8. 8782586 - Method, system, and program product for routing an integrated circuit to be manufactured by doubled patterning (2014-07-15),

9. 8782570 - Methods, systems, and articles of manufacture for implementing a physical electronic circuit design with multiple-patterning techniques (2014-07-15),

10. 8762908 - Static timing analysis with design-specific on chip variation de-rating factors (2014-06-24),

11. 8336010 - Design-specific on chip variation de-rating factors for static timing analysis of integrated circuits (2012-12-18),

12. 8151229 - System and method of computing pin criticalities under process variations for timing analysis and optimization (2012-04-03),

13. 8086978 - Method and system for performing statistical leakage characterization, analysis, and modeling (2011-12-27),

14. 8069432 - Method and system for performing statistical leakage characterization, analysis, and modeling (2011-11-29),

Title: Vassilios Constantinos Gerousis: Innovator in Integrated Circuit Design

Introduction

Vassilios Constantinos Gerousis is a prominent inventor based in San Jose, California. He has made significant contributions to the field of integrated circuit design, holding a total of 14 patents. His work focuses on enhancing the efficiency and functionality of electronic designs.

Latest Patents

One of his latest patents is for an integrated circuit power distribution network. This innovation involves a stack of layers formed on a substrate, which includes standard cells with parallel gate structures. Each cell is equipped with an internal power pin that supplies a reference voltage. The design features metal layers that route signals between cells, with lines oriented orthogonally to those in adjacent layers. Another notable patent is for a method and system that implements efficient trim data representation for electronic designs. This approach improves the management of gap shapes in layouts by deriving properties from adjacent objects, streamlining the design process.

Career Highlights

Throughout his career, Vassilios has worked with leading companies in the technology sector, including Cadence Design Systems, Inc. and Imec Vzw. His expertise in integrated circuit design has positioned him as a valuable asset in the industry.

Collaborations

Vassilios has collaborated with notable professionals in his field, including Hongliang Chang and Shuo Zhang. These partnerships have contributed to the advancement of his innovative projects.

Conclusion

Vassilios Constantinos Gerousis is a distinguished inventor whose work in integrated circuit design has led to numerous patents and advancements in electronic design. His contributions continue to influence the technology landscape significantly.

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